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Searched refs:LZ (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dselect-ctlz-to-cttz.ll63 ; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[AND]], i1 true), !range [[RNG0]]
64 ; CHECK-NEXT: [[SUB1:%.*]] = xor i32 [[LZ]], 31
132 ; CHECK-NEXT: [[SUB1:%.*]] = xor i32 [[LZ]], 31
133 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 [[LZ]], i32 [[SUB1]]
151 ; CHECK-NEXT: [[SUB11:%.*]] = or i64 [[LZ]], 64
152 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i64 [[LZ]], i64 [[SUB11]]
170 ; CHECK-NEXT: [[SUB1:%.*]] = xor i64 [[LZ]], 63
171 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i64 [[LZ]], i64 [[SUB1]]
189 ; CHECK-NEXT: [[SUB1:%.*]] = xor i64 [[LZ]], 63
190 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i64 [[LZ]], i64 [[SUB1]]
[all …]
H A Dcmp-intrinsic.ll119 ; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), [[RNG0:!range …
120 ; CHECK-NEXT: store i32 [[LZ]], i32* [[P:%.*]], align 4
121 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[LZ]], 24
172 ; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), [[RNG0]]
173 ; CHECK-NEXT: store i32 [[LZ]], i32* [[P:%.*]], align 4
215 ; CHECK-NEXT: [[LZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false)
216 ; CHECK-NEXT: store <2 x i32> [[LZ]], <2 x i32>* [[P:%.*]], align 8
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp271 unsigned LZ = countLeadingZeros(Imm); in expandMOVImmSimple() local
274 LastShift = ((63 - LZ) / 16) * 16; in expandMOVImmSimple()
H A DAArch64ISelLowering.cpp13736 unsigned LZ = countLeadingZeros((uint64_t)Val); in shouldConvertConstantLoadToIntImm() local
13737 unsigned Shift = (63 - LZ) / 16; in shouldConvertConstantLoadToIntImm()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp977 if ((LZ + FO + TZ) > 48) { in selectI64ImmDirect()
998 if ((LZ + TO) > 48) { in selectI64ImmDirect()
1006 getI32Imm(48 - LZ), getI32Imm(LZ)); in selectI64ImmDirect()
1024 if ((LZ + FO + TO) > 48) { in selectI64ImmDirect()
1076 if ((LZ + FO + TZ) > 32) { in selectI64ImmDirect()
1090 if ((LZ + TO) > 32) { in selectI64ImmDirect()
1100 getI32Imm(32 - LZ), getI32Imm(LZ)); in selectI64ImmDirect()
1108 if ((LZ + FO + TO) > 32) { in selectI64ImmDirect()
1162 unsigned FO = countLeadingOnes<uint64_t>(LZ == 64 ? 0 : (Imm << LZ)); in selectI64ImmDirectPrefix()
1214 if ((LZ + TO) > 30) { in selectI64ImmDirectPrefix()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/DebugInfo/PDB/
H A DPDBTypes.h163 LZ, enumerator
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp1459 uint64_t LZ = alignDown(Known.countMinLeadingZeros(), 8); in visitCallInst() local
1464 if (BW - LZ - TZ == 8) { in visitCallInst()
1465 assert(LZ != TZ && "active byte cannot be in the middle"); in visitCallInst()
1466 if (LZ > TZ) // -> shl(x) if the "active byte" is in the low part of x in visitCallInst()
1468 IIOperand, ConstantInt::get(IIOperand->getType(), LZ - TZ)); in visitCallInst()
1471 IIOperand, ConstantInt::get(IIOperand->getType(), TZ - LZ)); in visitCallInst()
/llvm-project-15.0.7/llvm/lib/DebugInfo/PDB/
H A DPDBExtras.cpp343 CASE_OUTPUT_ENUM_CLASS_NAME(PDB_SourceCompression, LZ, OS) in dumpPDBSourceCompression()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h345 MIMGBaseOpcode LZ; member
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1135 uint32_t LZ = countLeadingZeros(Mask); in ppAddrRewriteAndSrl() local
1137 if (TZ + M1 + LZ != 32) in ppAddrRewriteAndSrl()
1143 if (LZ > CV) in ppAddrRewriteAndSrl()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td110 MIMGBaseOpcode LZ = lz;
116 let Fields = ["L", "LZ"];
1445 // L to LZ Optimization Mapping
H A DAMDGPUInstCombineIntrinsic.cpp162 AMDGPU::getImageDimIntrinsicByBaseOpcode(LZMappingInfo->LZ, in simplifyAMDGCNImageIntrinsic()
H A DAMDGPUISelLowering.cpp3072 unsigned LZ = Known.countMinLeadingZeros(); in performShlCombine() local
3073 if (LZ < RHSVal) in performShlCombine()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DScalarEvolution.cpp3379 unsigned LZ = RHSC->getAPInt().countLeadingZeros(); in getUDivExpr() local
3380 unsigned MaxShiftAmt = getTypeSizeInBits(Ty) - LZ - 1; in getUDivExpr()
7559 unsigned LZ = A.countLeadingZeros(); in createSCEV() local
7567 APInt::getLowBitsSet(BitWidth, BitWidth - LZ - TZ).shl(TZ); in createSCEV()
7568 if ((LZ != 0 || TZ != 0) && !((~A & ~Known.Zero) & EffectiveMask)) { in createSCEV()
7590 IntegerType::get(getContext(), BitWidth - LZ - TZ)), in createSCEV()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5951 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); in lowerU64ToF32BitOps() local
5954 auto Sub = MIRBuilder.buildSub(S32, K, LZ); in lowerU64ToF32BitOps()
5960 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ); in lowerU64ToF32BitOps()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ196.td708 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LZ(DR|ER)$")>;
H A DSystemZScheduleZEC12.td746 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LZ(DR|ER)$")>;
H A DSystemZScheduleZ13.td776 def : InstRW<[WLat1, FXb, NormalGr], (instregex "LZ(DR|ER)$")>;
H A DSystemZScheduleZ16.td814 def : InstRW<[WLat1, FXb, NormalGr], (instregex "LZ(DR|ER)$")>;
H A DSystemZScheduleZ15.td813 def : InstRW<[WLat1, FXb, NormalGr], (instregex "LZ(DR|ER)$")>;
H A DSystemZScheduleZ14.td796 def : InstRW<[WLat1, FXb, NormalGr], (instregex "LZ(DR|ER)$")>;
/llvm-project-15.0.7/clang-tools-extra/clang-tidy/misc/ConfusableTable/
H A Dconfusables.txt2762 02AB ; 006C 007A ; MA # ( ʫ → lz ) LATIN SMALL LETTER LZ DIGRAPH → LATIN SMALL LETTER L, LATIN SMAL…