| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandImm.cpp | 81 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
96 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) }); in tryToreplicateChunks()
227 AArch64_AM::getShifterImm(AArch64_AM::LSL, in trySequenceOfOnes()
236 AArch64_AM::getShifterImm(AArch64_AM::LSL, in trySequenceOfOnes()
279 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImmSimple()
297 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImmSimple()
370 AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) }); in expandMOVImm()
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| H A D | AArch64SchedPredAmpere.td | 16 // Check for a LSL shift <= 4
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| H A D | AArch64SchedPredicates.td | 48 def CheckShiftLSL : CheckImmOperand_s<3, "AArch64_AM::LSL">;
233 // ORR Rd, ZR, Rm, LSL #0
287 // MOVI Vd, #0, LSL #0
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| H A D | AArch64RegisterInfo.td | 1132 // LSL(8|16|32|64)
1133 def ZPR#RegWidth#AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", RegWidth, 8>;
1134 def ZPR#RegWidth#AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", RegWidth, 16>;
1135 def ZPR#RegWidth#AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", RegWidth, 32>;
1136 def ZPR#RegWidth#AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", RegWidth, 64>;
1137 def ZPR#RegWidth#ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 8>;
1138 def ZPR#RegWidth#ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 16>;
1139 def ZPR#RegWidth#ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 32>;
1140 def ZPR#RegWidth#ExtLSL64 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 64>;
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| H A D | AArch64ExpandPseudoInsts.cpp | 990 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in expandMI()
1186 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0), in expandMI()
1191 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0), in expandMI()
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| H A D | AArch64FastISel.cpp | 720 Addr.setExtendType(AArch64_AM::LSL); in computeAddress()
802 Addr.setExtendType(AArch64_AM::LSL); in computeAddress()
847 Addr.setExtendType(AArch64_AM::LSL); in computeAddress()
1057 Addr.getOffsetReg(), AArch64_AM::LSL, in simplifyAddress()
1238 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL, in emitAddSub()
1252 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break; in emitAddSub()
1358 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1720 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitLogicalOp_rs()
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| H A D | AArch64SchedNeoverseN2.td | 1601 (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]$",
1602 "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]$",
1603 "^(ASR|LSL|LSR)_ZPmI_[BHSD]$",
1604 "^(ASR|LSL|LSR)_ZPmZ_[BHSD]$",
1605 "^(ASR|LSL|LSR)_ZZI_[BHSD]$",
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| /llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/ |
| H A D | m7-int.s | 9 adc.w r0, r1, r2, LSL #1
10 adcs.w r0, r1, r2, LSL #1
20 add.w r0, r1, r2, LSL #1
21 adds.w r0, r1, r2, LSL #1
31 add.w r0, sp, r1, LSL #1
39 and.w r0, r1, r2, LSL #1
62 cmn.w r0, r1, LSL #1
68 cmp.w r0, r1, LSL #1
181 mvn.w r0, r1, LSL #1
182 mvns.w r0, r1, LSL #1
[all …]
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| H A D | m4-int.s | 9 adc.w r0, r1, r2, LSL #1
10 adcs.w r0, r1, r2, LSL #1
20 add.w r0, sp, r1, LSL #1
21 adds.w r0, sp, r1, LSL #1
31 add.w r0, r1, r2, LSL #1
41 and.w r0, r1, r2, LSL #1
64 cmn.w r0, r1, LSL #1
70 cmp.w r0, r1, LSL #1
188 mvn.w r0, r1, LSL #1
189 mvns.w r0, r1, LSL #1
[all …]
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | unpredictable-LSL-regform.txt | 9 # A8.6.89 LSL (register)
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| H A D | thumb1.txt | 235 # LSL (immediate)
245 # LSL (register)
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| H A D | invalid-armv7.txt | 200 # To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1…
204 # A8.6.88 LSL (immediate)
233 # A8.6.89 LSL (register): Inst{7-4} = 0b0001
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 35 LSL = 0, enumerator
56 case AArch64_AM::LSL: return "lsl"; in getShiftExtendName()
77 case 0: return AArch64_AM::LSL; in getShiftType()
105 case AArch64_AM::LSL: STEnc = 0; break; in getShifterImm()
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| H A D | AArch64MCCodeEmitter.cpp | 265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
543 assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL && in getImm8OptLsl()
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | unpred-control-flow-in-it-block.s | 39 ldreq pc, [r0, r1, LSL #1]
55 tbheq [r0, r1, LSL #1]
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| H A D | basic-thumb-instructions.s | 351 @ LSL (immediate)
367 @ LSL (register)
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 38 LSL, ///< Logical shift left. enumerator
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| H A D | AVRInstrInfo.td | 58 def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
1848 // 8-bit LSL is an alias of ADD Rd, Rd
2104 // LSL Rd
2108 def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8 : $rd, GPR8 : $rd)>;
2525 // Lowering of 'lsl' node to 'LSL' instruction.
2526 // LSL is an alias of 'ADD Rd, Rd'
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| /llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM64/ |
| H A D | EmulateInstructionARM64.cpp | 84 static inline uint64_t LSL(uint64_t x, integer shift) { in LSL() function
765 idx = LSL(llvm::SignExtend64<7>(imm7), scale); in EmulateLDPSTP()
940 offset = LSL(Bits32(opcode, 21, 10), size); in EmulateLDRSTRImm()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1336 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1383 ET == AArch64_AM::LSL) && in isExtend()
1402 ET == AArch64_AM::LSL) && in isExtendLSL64()
1431 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1453 if (ST != AArch64_AM::LSL) in isMovImm32Shifter()
1465 if (ST != AArch64_AM::LSL) in isMovImm64Shifter()
1477 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecShifter()
1487 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecHalfWordShifter()
1899 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
1907 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX; in addExtend64Operands()
[all …]
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-interleaved-ld-combine.ll | 70 ; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #2
71 ; AS-DAG: add [[ADD:x[0-9]+]], [[LSL]], #64
132 ; AS-DAG: lsl [[LSL:x[0-9]+]], x1, #2
134 ; AS-DAG: and [[AND:x[0-9]+]], [[LSL]], #0xfffffffffffffff0
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| /llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/ |
| H A D | ARMUtils.h | 100 static inline uint32_t LSL(const uint32_t value, const uint32_t amount, in LSL() function
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| /llvm-project-15.0.7/llvm/test/ExecutionEngine/JITLink/AArch64/ |
| H A D | ELF_aarch64_relocations.s | 147 # The immediate value should be the symbol address right shifted according to LSL value
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2519 LatticeCell LSL, LSH; in evaluateHexRSEQ32() local
2520 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH)) in evaluateHexRSEQ32()
2522 if (LSL.isProperty() || LSH.isProperty()) in evaluateHexRSEQ32()
2525 unsigned LN = LSL.size(), HN = LSH.size(); in evaluateHexRSEQ32()
2528 bool Eval = constToInt(LSL.Values[i], LoVs[i]); in evaluateHexRSEQ32()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 551 LSL, enumerator
|