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Searched refs:LMul (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td114 vti.LMul, vti.AVL, vti.RegClass>;
117 vti.LMul, vti.AVL, vti.RegClass,
128 vti.LMul, vti.AVL, vti.RegClass,
155 vti.LMul, vti.AVL, vti.RegClass>;
255 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX)
388 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
402 (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX)
590 defvar suffix = vti.LMul.MX;
681 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
796 (!cast<Instruction>("PseudoVMOR_MM_"#mti.LMul.MX)
[all …]
H A DRISCVInstrInfoVVLPatterns.td702 (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
711 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
728 (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)
841 defvar suffix = vti.LMul.MX;
911 defvar suffix = vti.LMul.MX;
1194 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)
1202 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX)
1409 fvti.LMul.MX)
1415 fvti.LMul.MX # "_TU")
1573 defvar vlmul = vti.LMul;
[all …]
H A DRISCVInstrInfo.cpp294 LMul = RISCVII::LMUL_1; in copyPhysReg()
297 LMul = RISCVII::LMUL_2; in copyPhysReg()
300 LMul = RISCVII::LMUL_4; in copyPhysReg()
303 LMul = RISCVII::LMUL_8; in copyPhysReg()
308 LMul = RISCVII::LMUL_1; in copyPhysReg()
313 LMul = RISCVII::LMUL_2; in copyPhysReg()
318 LMul = RISCVII::LMUL_4; in copyPhysReg()
323 LMul = RISCVII::LMUL_1; in copyPhysReg()
328 LMul = RISCVII::LMUL_2; in copyPhysReg()
333 LMul = RISCVII::LMUL_1; in copyPhysReg()
[all …]
H A DRISCVInstrInfoVPseudos.td188 LMULInfo LMul = M;
298 LMULInfo LMul = M;
1622 let VLMul = mti.LMul.value in {
1694 let VLMul = mti.LMul.value in {
1746 let VLMul = mti.LMul.value in {
1758 let VLMul = mti.LMul.value in {
1771 let VLMul = mti.LMul.value in {
1795 let VLMul = mti.LMul.value in {
3662 defvar vlmul = vti.LMul;
4168 vti.Log2SEW, vti.LMul,
[all …]
H A DRISCVInsertVSETVLI.cpp286 unsigned LMul; in getSEWLMULRatio() local
288 std::tie(LMul, Fractional) = RISCVVType::decodeVLMUL(VLMul); in getSEWLMULRatio()
291 LMul = Fractional ? (8 / LMul) : (LMul * 8); in getSEWLMULRatio()
294 return (SEW * 8) / LMul; in getSEWLMULRatio()
1279 unsigned LMul; in hasFixedResult() local
1281 std::tie(LMul, Fractional) = RISCVVType::decodeVLMUL(Info.getVLMUL()); in hasFixedResult()
1284 return ST.getRealMinVLen() / LMul >= AVLInBits; in hasFixedResult()
1285 return ST.getRealMinVLen() * LMul >= AVLInBits; in hasFixedResult()
H A DRISCVISelLowering.h576 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
H A DRISCVISelLowering.cpp1472 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) { in getRegClassIDForLMUL() argument
1473 switch (LMul) { in getRegClassIDForLMUL()
1650 unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen); in useRVVForFixedLengthVectorVT() local
1652 if (LMul > Subtarget.getMaxLMULForFixedLengthVectors()) in useRVVForFixedLengthVectorVT()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.cpp164 unsigned LMul; in printVType() local
166 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType)); in printVType()
172 OS << LMul; in printVType()