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Searched refs:LDRD (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dgpr-paired-spill.ll1 …e=armv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD
2 …rmv4-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITHOUT-LDRD
19 ; CHECK-WITH-LDRD-DAG: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
20 ; CHECK-WITH-LDRD-DAG: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
22 ; CHECK-WITH-LDRD-DAG: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]
23 ; CHECK-WITH-LDRD-DAG: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp]
27 ; CHECK-WITHOUT-LDRD-DAG: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}}
28 ; CHECK-WITHOUT-LDRD-DAG: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
29 ; CHECK-WITHOUT-LDRD-DAG: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
33 ; CHECK-WITHOUT-LDRD-DAG: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
[all …]
H A Dload_store_opt_kill.mir12 $r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg
H A Dldrd.ll22 ; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base
36 ; able to generate an LDRD pair here, but this is highly sensitive to
40 ; R0/R1/R2 live as the three arguments, forcing the LDRD's odd
41 ; destination into R3. We then sensibly split LDRD again rather then
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dunpredictable-LDRD-arm.txt8 # A8.6.68 LDRD (register)
H A Dldrd-armv4.txt9 # A8.6.68 LDRD (register)
H A Dinvalid-thumbv7.txt62 # A8.6.66 LDRD (immediate)
63 # if Rn = '1111' then SEE LDRD (literal)
64 # A8.6.67 LDRD (literal)
H A Dmemory-arm-instructions.txt105 # LDRD (immediate)
125 # FIXME: LDRD (label)
129 # LDRD (register)
H A Dthumb2.txt674 # LDRD(immediate)
702 # FIXME: LDRD(literal)
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
1766 if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8) in FixInvalidRegPairOp()
1779 (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3(); in FixInvalidRegPairOp()
1781 bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) && in FixInvalidRegPairOp()
1788 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8; in FixInvalidRegPairOp()
2268 NewOpc = ARM::LDRD; in CanFormLdStDWord()
H A DARMISelLowering.h359 LDRD, enumerator
H A DARMScheduleA57.td396 def : InstRW<[A57WriteLdrAm3X2, A57WriteLdrAm3X2], (instregex "LDRD$")>;
442 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm.
490 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm.
H A DARMBaseInstrInfo.cpp1426 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD)); in loadRegFromStackSlot()
1957 case ARM::LDRD: in areLoadsFromSameBasePtr()
1978 case ARM::LDRD: in areLoadsFromSameBasePtr()
3583 case ARM::LDRD: { in getNumMicroOpsSwiftLdSt()
H A DARMScheduleR52.td296 "t2LDRpci_pic", "tLDRS(B|H)", "t2LDRDi8", "LDRD$", "LDA", "t2LDA")>;
H A DARMScheduleSwift.td376 (instregex "t2LDRDi8", "LDRD$")>;
H A DARMExpandPseudoInsts.cpp3122 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) in ExpandMI()
H A DARMInstrInfo.td249 def ARMldrd : SDNode<"ARMISD::LDRD", SDT_ARMldrd, [SDNPHasChain, SDNPMayLoad, SDNPMemOperan…
2839 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
H A DARMISelDAGToDAG.cpp4029 case ARMISD::LDRD: { in Select()
H A DARMISelLowering.cpp1723 MAKE_CASE(ARMISD::LDRD) in getTargetNodeName()
10019 ARMISD::LDRD, dl, DAG.getVTList({MVT::i32, MVT::i32, MVT::Other}), in LowerLOAD()
/llvm-project-15.0.7/llvm/docs/
H A DAtomics.rst214 ``LDRD`` on ARM without LPAE, or not naturally-aligned ``LDRD`` on LPAE ARM).
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2226 case ARM::LDRD: in DecodeAddrMode3Instruction()
2260 case ARM::LDRD: in DecodeAddrMode3Instruction()
2342 case ARM::LDRD: in DecodeAddrMode3Instruction()
2355 case ARM::LDRD: in DecodeAddrMode3Instruction()
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-thumb2-instructions.s1161 @ LDRD
1185 @ FIXME: LDRD(literal)
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td2598 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>;
2778 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr",
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7734 case ARM::LDRD: in validateInstruction()