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Searched refs:LAR (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopPassManager.cpp221 LoopStandardAnalysisResults LAR = {AM.getResult<AAManager>(F), in run() local
259 PI.pushBeforeNonSkippedPassCallback([&LAR, &LI](StringRef PassID, Any IR) { in run()
270 assert(L->isRecursivelyLCSSAForm(LAR.DT, LI) && in run()
297 PassPA = Pass->run(*L, LAM, LAR, Updater); in run()
306 if (LAR.MSSA && !PassPA.getChecker<MemorySSAAnalysis>().preserved()) in run()
313 LAR.DT.verify(); in run()
315 LAR.LI.verify(LAR.DT); in run()
317 LAR.SE.verify(); in run()
318 if (LAR.MSSA && VerifyMemorySSA) in run()
319 LAR.MSSA->verifyMemorySSA(); in run()
H A DLoopVersioningLICM.cpp665 LoopStandardAnalysisResults &LAR, in run() argument
667 AliasAnalysis *AA = &LAR.AA; in run()
668 ScalarEvolution *SE = &LAR.SE; in run()
669 DominatorTree *DT = &LAR.DT; in run()
670 LoopInfo *LI = &LAR.LI; in run()
675 return AM.getResult<LoopAccessAnalysis>(*L, LAR); in run()
/llvm-project-15.0.7/llvm/include/llvm/Transforms/Scalar/
H A DLoopVersioningLICM.h22 LoopStandardAnalysisResults &LAR, LPMUpdater &U);
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DLoopVectorizationLegality.cpp909 const OptimizationRemarkAnalysis *LAR = LAI->getReport(); in canVectorizeMemory() local
910 if (LAR) { in canVectorizeMemory()
913 "loop not vectorized: ", *LAR); in canVectorizeMemory()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DScalarEvolution.cpp11565 const auto *LAR = cast<SCEVAddRecExpr>(Less); in computeConstantDifference() local
11568 if (LAR->getLoop() != MAR->getLoop()) in computeConstantDifference()
11573 if (!LAR->isAffine() || !MAR->isAffine()) in computeConstantDifference()
11579 Less = LAR->getStart(); in computeConstantDifference()
11935 const SCEVAddRecExpr *LAR = dyn_cast<SCEVAddRecExpr>(LHS); in IsKnownPredicateViaAddRecStart() local
11936 if (!LAR) in IsKnownPredicateViaAddRecStart()
11941 if (LAR->getLoop() != RAR->getLoop()) in IsKnownPredicateViaAddRecStart()
11943 if (!LAR->isAffine() || !RAR->isAffine()) in IsKnownPredicateViaAddRecStart()
11946 if (LAR->getStepRecurrence(SE) != RAR->getStepRecurrence(SE)) in IsKnownPredicateViaAddRecStart()
11951 if (!LAR->getNoWrapFlags(NW) || !RAR->getNoWrapFlags(NW)) in IsKnownPredicateViaAddRecStart()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SchedSkylakeClient.td930 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1337 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
H A DX86SchedBroadwell.td1280 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1375 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
H A DX86SchedHaswell.td1477 def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
1484 def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
H A DX86SchedSkylakeServer.td1050 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1766 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
H A DX86SchedIceLake.td1068 def: InstRW<[ICXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1785 def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm",
H A DX86ScheduleBdVer2.td314 def : InstRW<[PdWriteLARrr], (instregex "LAR(16|32|64)rr",