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Searched refs:LADD (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/mlir/test/Conversion/TosaToArith/
H A Dtosa-to-arith.mlir58 // CHECK-DAG: %[[LADD:.+]] = arith.addi %[[DLOW]], %[[HALF]]
59 // CHECK-DAG: %[[LLO:.+]] = arith.cmpi ugt, %[[DLOW]], %[[LADD]]
72 // CHECK-DAG: %[[LOR:.+]] = arith.shrui %[[LADD]], %[[S32]]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h53 LADD, enumerator
H A DXCoreISelDAGToDAG.cpp162 case XCoreISD::LADD: { in Select()
H A DXCoreISelLowering.cpp57 case XCoreISD::LADD : return "XCoreISD::LADD"; in getTargetNodeName()
717 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : in ExpandADDSUB()
1631 case XCoreISD::LADD: { in PerformDAGCombine()
1641 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); in PerformDAGCombine()
1729 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1); in PerformDAGCombine()
1820 case XCoreISD::LADD: in computeKnownBitsForTargetNode()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h785 LADD, enumerator
H A DX86InstrInfo.td270 def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags,
H A DX86ISelLowering.cpp31628 NewOpc = X86ISD::LADD; in lowerAtomicArithWithLOCK()
33530 NODE_NAME_CASE(LADD) in getTargetNodeName()