| /llvm-project-15.0.7/clang/test/CodeGen/X86/ |
| H A D | sse42-builtins.c | 11 int test_mm_cmpestra(__m128i A, int LA, __m128i B, int LB) { in test_mm_cmpestra() argument 14 return _mm_cmpestra(A, LA, B, LB, 7); in test_mm_cmpestra() 17 int test_mm_cmpestrc(__m128i A, int LA, __m128i B, int LB) { in test_mm_cmpestrc() argument 20 return _mm_cmpestrc(A, LA, B, LB, 7); in test_mm_cmpestrc() 23 int test_mm_cmpestri(__m128i A, int LA, __m128i B, int LB) { in test_mm_cmpestri() argument 26 return _mm_cmpestri(A, LA, B, LB, 7); in test_mm_cmpestri() 32 return _mm_cmpestrm(A, LA, B, LB, 7); in test_mm_cmpestrm() 35 int test_mm_cmpestro(__m128i A, int LA, __m128i B, int LB) { in test_mm_cmpestro() argument 38 return _mm_cmpestro(A, LA, B, LB, 7); in test_mm_cmpestro() 44 return _mm_cmpestrs(A, LA, B, LB, 7); in test_mm_cmpestrs() [all …]
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| /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/ |
| H A D | frame-26.mir | 95 renamable $r3d = LA %stack.0, 40, $noreg 99 renamable $r14d = LA %stack.0, 72, $noreg 100 renamable $r13d = LA %stack.0, 80, $noreg 101 renamable $r12d = LA %stack.0, 56, $noreg 102 renamable $r10d = LA %stack.0, 0, $noreg 104 renamable $r9d = LA %stack.0, 64, $noreg 105 renamable $r8d = LA %stack.0, 88, $noreg 170 renamable $r3d = LA %stack.0, 40, $noreg 177 renamable $r10d = LA %stack.0, 0, $noreg 179 renamable $r9d = LA %stack.0, 64, $noreg [all …]
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| H A D | machinelicm-sunk-kill-flags.mir | 32 ; CHECK-NEXT: [[LA:%[0-9]+]]:gr64bit = LA [[LARL]], 49, $noreg 38 ; CHECK-NEXT: $r3d = COPY [[LA]] 44 ; CHECK-NEXT: $r3d = COPY [[LA]] 53 %0:gr64bit = LA killed %1, 49, $noreg
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| H A D | clear-liverange-spillreg.mir | 227 %7 = LA %6, 64, %41 294 %64 = LA %62, 0, %63 300 %71 = LA %70, 2, $noreg 303 %74 = LA %70, 2, %67 316 %84 = LA %62, 64, %63 322 %90 = LA %70, 0, %67 325 %92 = LA %72, 64, %63 327 %94 = LA %86, 6, %63 329 %96 = LA %82, 0, %63 350 %120 = LA %120, 1, $noreg
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| H A D | cond-move-regalloc-hints.mir | 227 %60:addr64bit = nuw nsw LA %10, 1, $noreg 239 %25:gr64bit = LA %64, 4, $noreg 244 %63:addr64bit = LA %63, 1, $noreg 275 %56:addr64bit = LA %56, 1, $noreg
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| H A D | regcoal-subranges-update.mir | 68 ; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg 90 %1:gr64bit = nuw nsw LA killed %0, 1, $noreg
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| H A D | regcoal-undef-lane-4-rm-cp-commuting-def.mir | 62 ; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 6, $noreg 122 %5:gr64bit = nuw nsw LA killed %0, 6, $noreg
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| H A D | load-and-test-RA-hints.mir | 159 %22:addr64bit = LA %22, 16, $noreg 160 %21:addr64bit = LA %21, 16, $noreg
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| H A D | cond-move-08.mir | 143 %28:addr64bit = nuw nsw LA %28, 4, $noreg 144 %26:addr64bit = LA %26, 16, $noreg
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| H A D | subregliveness-06.mir | 144 %4:addr64bit = LA %stack.1.tmp2, 96, $noreg 154 %14:gr64bit = LA %stack.0.tmp, 0, $noreg 169 %27:addr64bit = LA %26, 1, %6
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| /llvm-project-15.0.7/lldb/test/API/lang/cpp/stl/ |
| H A D | TestStdCXXDisassembly.py | 74 LA = match.group(1) 77 print("load address:", LA) 79 if SA and LA: 80 if int(LA, 16) > int(SA, 16): 81 self.runCmd("disassemble -s %s -e %s" % (SA, LA)) 82 SA = LA
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| /llvm-project-15.0.7/clang/test/CodeGen/ |
| H A D | attr-target-crc32-x86.c | 43 int __attribute__((target("sse4.2,no-crc32,crc32"))) test6(__m128i A, int LA, __m128i B, int LB) { in test6() argument 44 return _mm_cmpestra(A, LA, B, LB, 7); in test6() 49 int __attribute__((target("no-crc32,crc32,sse4.2"))) test7(__m128i A, int LA, __m128i B, int LB) { in test7() argument 50 return _mm_cmpestra(A, LA, B, LB, 7); in test7()
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| /llvm-project-15.0.7/bolt/lib/Passes/ |
| H A D | DataflowInfoManager.cpp | 41 if (LA) in getLivenessAnalysis() 42 return *LA; in getLivenessAnalysis() 44 LA.reset(new LivenessAnalysis(*RA, BF, AllocatorId)); in getLivenessAnalysis() 45 LA->run(); in getLivenessAnalysis() 46 return *LA; in getLivenessAnalysis() 49 void DataflowInfoManager::invalidateLivenessAnalysis() { LA.reset(nullptr); } in invalidateLivenessAnalysis()
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| H A D | JTFootprintReduction.cpp | 154 LivenessAnalysis &LA = Info.getLivenessAnalysis(); in tryOptimizeNonPIC() local 155 MCPhysReg Reg = LA.scavengeRegAfter(&*Inst); in tryOptimizeNonPIC()
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| /llvm-project-15.0.7/clang/lib/Headers/ |
| H A D | smmintrin.h | 1720 #define _mm_cmpestrm(A, LA, B, LB, M) \ argument 1721 ((__m128i)__builtin_ia32_pcmpestrm128((__v16qi)(__m128i)(A), (int)(LA), \ 1779 #define _mm_cmpestri(A, LA, B, LB, M) \ argument 1780 ((int)__builtin_ia32_pcmpestri128((__v16qi)(__m128i)(A), (int)(LA), \ 2082 #define _mm_cmpestra(A, LA, B, LB, M) \ argument 2083 ((int)__builtin_ia32_pcmpestria128((__v16qi)(__m128i)(A), (int)(LA), \ 2136 #define _mm_cmpestrc(A, LA, B, LB, M) \ argument 2137 ((int)__builtin_ia32_pcmpestric128((__v16qi)(__m128i)(A), (int)(LA), \ 2189 #define _mm_cmpestro(A, LA, B, LB, M) \ argument 2190 ((int)__builtin_ia32_pcmpestrio128((__v16qi)(__m128i)(A), (int)(LA), \ [all …]
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | fp16-litpool3-arm.mir | 21 br i1 %tobool, label %LA, label %END 23 LA: ; preds = %entry 27 END: ; preds = %LA, %entry 86 # aligned. Here BB.1.LA has already an 8-byte alignment, and we are 89 #CHECK: bb.{{.*}}.LA (align 8): 103 bb.1.LA (align 8):
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| H A D | fp16-litpool2-arm.mir | 20 br i1 %tobool, label %LA, label %END 22 LA: ; preds = %entry 26 END: ; preds = %LA, %entry 83 #CHECK: bb.{{.*}}.LA (align 4): 97 bb.1.LA:
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| /llvm-project-15.0.7/llvm/lib/DebugInfo/DWARF/ |
| H A D | DWARFExpression.cpp | 72 for (uint16_t LA = DW_OP_lit0; LA <= DW_OP_lit31; ++LA) in getDescriptions() local 73 Descriptions[LA] = Desc(Op::Dwarf2); in getDescriptions() 74 for (uint16_t LA = DW_OP_reg0; LA <= DW_OP_reg31; ++LA) in getDescriptions() local 75 Descriptions[LA] = Desc(Op::Dwarf2); in getDescriptions() 76 for (uint16_t LA = DW_OP_breg0; LA <= DW_OP_breg31; ++LA) in getDescriptions() local 77 Descriptions[LA] = Desc(Op::Dwarf2, Op::SignedSizeLEB); in getDescriptions()
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| /llvm-project-15.0.7/clang/lib/Parse/ |
| H A D | ParseCXXInlineMethods.cpp | 704 void Parser::ParseLexedAttribute(LateParsedAttribute &LA, in ParseLexedAttribute() argument 712 AttrEnd.setEofData(LA.Toks.data()); in ParseLexedAttribute() 713 LA.Toks.push_back(AttrEnd); in ParseLexedAttribute() 717 LA.Toks.push_back(Tok); in ParseLexedAttribute() 724 if (LA.Decls.size() > 0) { in ParseLexedAttribute() 725 Decl *D = LA.Decls[0]; in ParseLexedAttribute() 733 if (LA.Decls.size() == 1) { in ParseLexedAttribute() 745 ParseGNUAttributeArgs(&LA.AttrName, LA.AttrNameLoc, Attrs, nullptr, in ParseLexedAttribute() 754 ParseGNUAttributeArgs(&LA.AttrName, LA.AttrNameLoc, Attrs, nullptr, in ParseLexedAttribute() 765 << &LA.AttrName; in ParseLexedAttribute() [all …]
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| /llvm-project-15.0.7/llvm/lib/ExecutionEngine/Orc/ |
| H A D | EPCGenericRTDyldMemoryManager.cpp | 172 ExecutorAddr LA(LoadAddr); in registerEHFrames() local 174 if (Alloc.RemoteCode.contains(LA) || Alloc.RemoteROData.contains(LA) || in registerEHFrames() 175 Alloc.RemoteRWData.contains(LA)) { in registerEHFrames() 176 Alloc.UnfinalizedEHFrames.push_back({LA, Size}); in registerEHFrames()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | FunctionComparator.cpp | 127 Attribute LA = *LI; in cmpAttrs() local 129 if (LA.isTypeAttribute() && RA.isTypeAttribute()) { in cmpAttrs() 130 if (LA.getKindAsEnum() != RA.getKindAsEnum()) in cmpAttrs() 131 return cmpNumbers(LA.getKindAsEnum(), RA.getKindAsEnum()); in cmpAttrs() 133 Type *TyL = LA.getValueAsType(); in cmpAttrs() 147 if (LA < RA) in cmpAttrs() 149 if (RA < LA) in cmpAttrs() 316 const ConstantArray *LA = cast<ConstantArray>(L); in cmpConstants() local 323 if (int Res = cmpConstants(cast<Constant>(LA->getOperand(i)), in cmpConstants()
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| /llvm-project-15.0.7/lldb/test/Shell/SymbolFile/DWARF/x86/ |
| H A D | limit-debug-info.s | 121 .long .LA-.Lsection_info # DW_AT_type 125 .LA: label
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| H A D | DW_AT_declaration-with-children.s | 199 .long .LA-.Lcu_begin0 # DW_AT_type 203 .LA: label 218 .long .LA-.Lcu_begin0 # DW_AT_type
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| H A D | debug-types-line-tables.s | 24 .long .LA # DW_AT_name 124 .LA: label
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| /llvm-project-15.0.7/bolt/include/bolt/Passes/ |
| H A D | DataflowInfoManager.h | 36 std::unique_ptr<LivenessAnalysis> LA; variable
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