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Searched refs:JR (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll31 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
42 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
52 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
62 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
72 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
82 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
92 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
103 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
118 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
134 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
[all …]
H A Dindirectbr.ll17 ; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR
22 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
28 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
H A Dload.ll31 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
96 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
124 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
194 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
259 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
287 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
358 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
423 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
451 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
586 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
[all …]
H A Dstore.ll30 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
95 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
164 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
229 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
298 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
363 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
440 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
529 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
614 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
679 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
[all …]
H A Dfptosi.ll44 ; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
55 ; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
85 ; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
97 ; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
120 ; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
235 ; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
246 ; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
276 ; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
288 ; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
311 ; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Deh-return32.ll46 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
86 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
H A Deh-return64.ll47 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
89 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/longbranch/
H A Dbranch-limits-int-microMIPS.mir164 ; PIC: JR $at {
259 ; PIC: JR $at {
354 ; PIC: JR $at {
449 ; PIC: JR $at {
544 ; PIC: JR $at {
635 ; PIC: JR $at {
730 ; PIC: JR $at {
825 ; PIC: JR $at {
H A Dbranch-limits-int.mir148 ; PIC: JR $at {
247 ; PIC: JR $at {
346 ; PIC: JR $at {
445 ; PIC: JR $at {
544 ; PIC: JR $at {
643 ; PIC: JR $at {
H A Dbranch-limits-fp-mips.mir110 ; PIC: JR $at {
214 ; PIC: JR $at {
H A Dbranch-limits-fp-micromips.mir109 ; PIC: JR $at {
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Hexagon/
H A Djr.txt2 # Hexagon Programmer's Reference Manual 11.3 JR
/llvm-project-15.0.7/third-party/benchmark/test/
H A Doutput_test_helper.cc393 benchmark::JSONReporter JR; in RunOutputTests() local
414 JR}, in RunOutputTests()
421 internal::TestReporter test_rep({&CR, &JR, &CSVR}); in RunOutputTests()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV60.td20 // | SLOT2 | XTYPE ALU32 J JR |
/llvm-project-15.0.7/llvm/test/MC/Lanai/
H A Dconditional_inst.s9 ! CHECK-NEXT: <MCInst #{{[0-9]+}} JR{{$}}
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp65 return MI.getOpcode() == Mips::JR; in isIndirectJump()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsBranchExpansion.cpp385 unsigned JR = ABI.IsN64() ? Mips::JR64 : Mips::JR; in buildProperJumpMI() local
394 JumpOp = HasR6 ? JIC : JR; in buildProperJumpMI()
H A DMipsInstrInfo.cpp469 case Mips::JR: in getEquivalentCompactForm()
549 case Mips::JR: in getEquivalentCompactForm()
880 case Mips::JR: in verifyInstruction()
H A DMipsAsmPrinter.cpp134 TmpInst0.setOpcode(Mips::JR); in emitPseudoIndirectBranch()
1112 EmitInstrReg(*STI, Mips::JR, Mips::S2); in EmitFPCallStub()
H A DMipsDelaySlotFiller.cpp752 (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || in searchRange()
H A DMipsInstrInfo.td2222 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>,
2277 def TAILCALLREG : TailCallReg<JR, GPR32Opnd>, ISA_MIPS1_NOT_32R6_64R6;
2280 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
2295 def PseudoIndirectBranch : PseudoIndirectBranchBase<JR, GPR32Opnd>,
2300 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
2686 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>, ISA_MIPS1;
H A DMipsScheduleP5600.td75 DERET, ERET, ERet, ERETNC, J, JR, JR_HB,
H A DMipsScheduleGeneric.td287 BLEZ, BLTZ, BLTZAL, J, JALX, JR, JR_HB, ERET,
H A DMips16InstrInfo.td754 // Format: JR ra MIPS16e
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td690 def JR : InstRR<0b101, (outs), (ins GPR:$Rs2), "bt\t$Rs2",