Searched refs:IsSignExt (Results 1 – 3 of 3) sorted by relevance
8396 bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL; in combineMUL_VLToVWMUL_VL() local8398 bool IsVWMULSU = IsSignExt && Op1.getOpcode() == RISCVISD::VZEXT_VL; in combineMUL_VLToVWMUL_VL()8399 if ((!IsSignExt && !IsZeroExt) || !Op0.hasOneUse()) in combineMUL_VLToVWMUL_VL()8451 if (IsSignExt && DAG.ComputeNumSignBits(Op1) > (ScalarBits - NarrowSize)) { in combineMUL_VLToVWMUL_VL()8457 IsVWMULSU = IsSignExt; in combineMUL_VLToVWMUL_VL()8470 unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in combineMUL_VLToVWMUL_VL()8480 WMulOpc = IsSignExt ? RISCVISD::VWMUL_VL : RISCVISD::VWMULU_VL; in combineMUL_VLToVWMUL_VL()
9162 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local9165 if (!IsSignExt && !IsZeroExt) in combineShiftToMULH()9173 unsigned ActiveBits = IsSignExt in combineShiftToMULH()9209 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
13924 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local13962 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine()13963 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()