| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/ |
| H A D | TargetTest.cpp | 68 Matcher<MCOperand> IsReg(unsigned Reg) { in IsReg() function
84 ElementsAre(IsReg(X86::RSP), IsImm(1), IsReg(0), IsImm(Offset), in IsMovValueToStack()
85 IsReg(0), IsImm(Value))); in IsMovValueToStack()
90 ElementsAre(IsReg(Reg), IsReg(X86::RSP), IsImm(1), IsReg(0), in IsMovValueFromStack()
91 IsImm(0), IsReg(0))); in IsMovValueFromStack()
96 ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size))); in IsStackAllocate()
101 ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size))); in IsStackDeallocate()
369 EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(0)); in TEST_F()
371 EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0)); in TEST_F()
382 EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0)); in TEST_F()
[all …]
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| H A D | SnippetGeneratorTest.cpp | 36 MATCHER(IsReg, "") { return arg.isReg(); }
131 AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()), in TEST_F()
132 ElementsAre(IsReg(), IsReg(), IsInvalid()))) in TEST_F()
174 AnyOf(ElementsAre(IsReg(), IsInvalid()), in TEST_F()
175 ElementsAre(IsInvalid(), IsReg()))); in TEST_F()
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| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/ |
| H A D | SnippetGeneratorTest.cpp | 30 MATCHER(IsReg, "") { return arg.isReg(); }
73 AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()), in TEST_F()
74 ElementsAre(IsReg(), IsReg(), IsInvalid()))) in TEST_F()
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| H A D | TargetTest.cpp | 36 Matcher<MCOperand> IsReg(unsigned Reg) { in IsReg() function
49 ElementsAre(IsReg(Reg), IsReg(ZeroReg), IsImm(Value))); in IsLoadLow16BitImm()
54 return AllOf(OpcodeIs(LUi), ElementsAre(IsReg(Reg), IsImm(Value))); in IsLoadHigh16BitImm()
60 ElementsAre(IsReg(Reg), IsReg(Reg), IsImm(Amount))); in IsShift()
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| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/PowerPC/ |
| H A D | SnippetGeneratorTest.cpp | 30 MATCHER(IsReg, "") { return arg.isReg(); }
73 AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()), in TEST_F()
74 ElementsAre(IsReg(), IsReg(), IsInvalid()))) in TEST_F()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 354 bool IsReg; variable
357 explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {} in RegOrConstant()
358 explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {} in RegOrConstant()
359 bool isReg() const { return IsReg; } in isReg()
360 bool isCst() const { return !IsReg; } in isCst()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsTargetStreamer.h | 102 const MCSymbol &Sym, bool IsReg);
291 const MCSymbol &Sym, bool IsReg) override;
356 const MCSymbol &Sym, bool IsReg) override;
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 146 const MCSymbol &Sym, bool IsReg) { in emitDirectiveCpsetup() argument
709 bool IsReg) { in emitDirectiveCpsetup() argument
713 if (IsReg) in emitDirectiveCpsetup()
1241 bool IsReg) { in emitDirectiveCpsetup() argument
1252 if (IsReg) { in emitDirectiveCpsetup()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.h | 148 static inline SIArgument createArgument(bool IsReg) { in createArgument()
149 if (IsReg) in createArgument()
150 return SIArgument(IsReg); in createArgument()
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