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Searched refs:IsAGPR (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUResourceUsageAnalysis.cpp233 bool IsAGPR = false; in analyzeResourceUsage() local
323 IsAGPR = true; in analyzeResourceUsage()
335 IsAGPR = true; in analyzeResourceUsage()
345 IsAGPR = true; in analyzeResourceUsage()
357 IsAGPR = true; in analyzeResourceUsage()
367 IsAGPR = true; in analyzeResourceUsage()
377 IsAGPR = true; in analyzeResourceUsage()
387 IsAGPR = true; in analyzeResourceUsage()
399 IsAGPR = true; in analyzeResourceUsage()
411 IsAGPR = true; in analyzeResourceUsage()
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H A DSILoadStoreOptimizer.cpp116 bool IsAGPR; member
650 IsAGPR = LSO.TRI->hasAGPRs(LSO.getDataRegClass(*MI)); in setMI()
2125 AddrList.front().IsAGPR == CI.IsAGPR && in addInstToMergeableList()
2181 if (CI.InstClass == DS_WRITE && CI.IsAGPR) { in collectMergeableInsts()
H A DSIRegisterInfo.cpp1292 const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC); in buildSpillLoadStore() local
1297 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()
1551 if (IsAGPR) { in buildSpillLoadStore()
1588 MIB.addReg(TmpOffsetVGPR, getKillRegState(IsLastSubReg && !IsAGPR)); in buildSpillLoadStore()
1614 if (!IsAGPR && NeedSuperRegDef) in buildSpillLoadStore()
1617 if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) { in buildSpillLoadStore()
H A DSIFixSGPRCopies.cpp270 bool IsAGPR = TRI->isAGPRClass(DstRC); in foldVGPRCopyIntoRegSequence() local
289 if (IsAGPR) { in foldVGPRCopyIntoRegSequence()
H A DSIInstrInfo.cpp5025 bool IsAGPR = RI.isAGPR(MRI, MO->getReg()); in isOperandLegal() local
5026 if (IsAGPR && !ST.hasMAIInsts()) in isOperandLegal()
5029 if (IsAGPR && in isOperandLegal()
5039 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isOperandLegal()
5043 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isOperandLegal()
5049 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isOperandLegal()
8478 bool IsAGPR = RI.isAGPR(MRI, DataReg); in enforceOperandRCAlignment() local
8480 IsAGPR ? &AMDGPU::AGPR_32RegClass : &AMDGPU::VGPR_32RegClass); in enforceOperandRCAlignment()
8483 MRI.createVirtualRegister(IsAGPR ? &AMDGPU::AReg_64_Align2RegClass in enforceOperandRCAlignment()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1501 bool IsAGPR = Val & 512; in decodeSrcOp() local
1505 return createRegOperand(IsAGPR ? getAgprClassId(Width) in decodeSrcOp()