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Searched refs:InputArg (Results 1 – 25 of 64) sorted by relevance

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/llvm-project-15.0.7/clang/include/clang/Driver/
H A DInputInfo.h32 InputArg, enumerator
38 const llvm::opt::Arg *InputArg; member
65 : Kind(InputArg), Act(nullptr), Type(_Type), BaseInput(_BaseInput) { in InputInfo()
66 Data.InputArg = _InputArg; in InputInfo()
70 : Kind(InputArg), Act(A), Type(GetActionType(A)), BaseInput(_BaseInput) { in InputInfo()
71 Data.InputArg = _InputArg; in InputInfo()
76 bool isInputArg() const { return Kind == InputArg; } in isInputArg()
89 return *Data.InputArg; in getInputArg()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCCState.h47 void PreAnalyzeCallResultForF128(const SmallVectorImpl<ISD::InputArg> &Ins,
64 PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins);
67 PreAnalyzeCallResultForVectorFloat(const SmallVectorImpl<ISD::InputArg> &Ins,
71 const SmallVectorImpl<ISD::InputArg> &Ins);
131 void PreAnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in PreAnalyzeFormalArguments()
139 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments()
151 void PreAnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, in PreAnalyzeCallResult()
161 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeCallResult()
H A DMipsCCState.cpp87 const SmallVectorImpl<ISD::InputArg> &Ins, in PreAnalyzeCallResultForF128()
112 const SmallVectorImpl<ISD::InputArg> &Ins, const Type *RetTy) { in PreAnalyzeCallResultForVectorFloat()
181 const SmallVectorImpl<ISD::InputArg> &Ins) { in PreAnalyzeFormalArgumentsForF128()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h123 const SmallVectorImpl<ISD::InputArg> &Ins,
129 const SmallVectorImpl<ISD::InputArg> &Ins,
135 const SmallVectorImpl<ISD::InputArg> &Ins,
144 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h146 const SmallVectorImpl<ISD::InputArg> &Ins,
152 const SmallVectorImpl<ISD::InputArg> &Ins,
158 const SmallVectorImpl<ISD::InputArg> &Ins,
164 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DMSP430ISelLowering.cpp446 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeVarArgs()
550 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeRetResult()
568 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments()
591 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
619 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCArguments()
809 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCCallTo()
937 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetCallingConv.h195 struct InputArg { struct
211 InputArg() = default; argument
212 InputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool used, in InputArg() argument
H A DCallingConvLower.h281 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
285 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeArguments()
320 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
523 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.h197 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
228 const SmallVectorImpl<ISD::InputArg> &Ins,
236 const SmallVectorImpl<ISD::InputArg> &Ins,
275 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCCState.h25 PreAnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
50 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments()
H A DPPCISelLowering.h1235 const SmallVectorImpl<ISD::InputArg> &Ins,
1241 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
1320 const SmallVectorImpl<ISD::InputArg> &Ins,
1328 const SmallVectorImpl<ISD::InputArg> &Ins,
1334 const SmallVectorImpl<ISD::InputArg> &Ins,
1357 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1361 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1365 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1376 const SmallVectorImpl<ISD::InputArg> &Ins,
1383 const SmallVectorImpl<ISD::InputArg> &Ins,
[all …]
H A DPPCCCState.cpp27 const SmallVectorImpl<ISD::InputArg> &Ins) { in PreAnalyzeFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.h86 const SmallVectorImpl<ISD::InputArg> &Ins,
100 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h148 const SmallVectorImpl<ISD::InputArg> &Ins,
156 const SmallVectorImpl<ISD::InputArg> &Ins,
212 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h125 const SmallVectorImpl<ISD::InputArg> &Ins,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
135 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h72 const SmallVectorImpl<ISD::InputArg> &Ins,
93 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.h82 const SmallVectorImpl<ISD::InputArg> &Ins,
96 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h56 const ISD::InputArg *Arg = nullptr) const;
63 const ISD::InputArg &Arg) const;
139 bool Signed, const ISD::InputArg *Arg = nullptr) const;
340 const SmallVectorImpl<ISD::InputArg> &Ins,
364 const SmallVectorImpl<ISD::InputArg> &Ins,
375 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
H A DR600ISelLowering.h43 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCallingConvLower.cpp82 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments()
159 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeCallResult()
261 const SmallVectorImpl<ISD::InputArg> &Ins, in resultsCompatible()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.h173 const SmallVectorImpl<ISD::InputArg> &Ins,
180 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/clang/lib/Driver/
H A DDriver.cpp3656 recordHostAction(HostAction, InputArg); in addDeviceDependencesToHostAction()
3710 recordHostAction(HostAction, InputArg); in addHostDependenceToDeviceActions()
3728 recordHostAction(HostAction, InputArg); in addHostDependenceToDeviceActions()
3766 recordHostAction(HostAction, InputArg); in appendTopLevelActions()
3789 recordHostAction(HostAction, InputArg); in appendTopLevelActions()
3929 const Arg *InputArg = I.second; in handleArguments() local
3938 if (InputArg->isClaimed()) in handleArguments()
3942 InputArg->claim(); in handleArguments()
4067 const Arg *InputArg = I.second; in BuildActions() local
4219 const Arg *InputArg = I.second; in BuildActions() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h123 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
190 const SmallVectorImpl<ISD::InputArg> &Ins,
211 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h1512 const SmallVectorImpl<ISD::InputArg> &Ins,
1517 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1534 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
1605 const SmallVectorImpl<ISD::InputArg> &Ins,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h51 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, in AnalyzeFormalArguments()

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