Searched refs:InitReg (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 1262 Register phi(Register LoopReg, Optional<Register> InitReg = {},
1450 if (InitReg) { in phi()
1451 auto I = Phis.find({LoopReg, InitReg.value()}); in phi()
1466 if (!InitReg) in phi()
1472 MI->getOperand(1).setReg(InitReg.value()); in phi()
1473 Phis.insert({{LoopReg, InitReg.value()}, R}); in phi()
1486 if (InitReg) { in phi()
1488 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
1493 .addReg(InitReg ? *InitReg : undef(RC)) in phi()
1497 if (!InitReg) in phi()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600MachineCFGStructurizer.cpp | 1287 Register InitReg = in improveSimpleJumpintoIf() local
1289 insertCondBranchBefore(LandBlk, I, R600::IF_PREDICATE_SET, InitReg, in improveSimpleJumpintoIf()
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| H A D | SIISelLowering.cpp | 3588 unsigned InitReg, unsigned ResultReg, unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
3604 .addReg(InitReg) in emitLoadM0FromVGPRLoop()
3836 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitIndirectSrc() local
3838 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg); in emitIndirectSrc()
3841 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset, in emitIndirectSrc()
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