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Searched refs:InVec (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dvector-mul.ll7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
27 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
60 define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
71 define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
82 define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
93 define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
104 define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
201 define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsse2-vector-shifts.ll8 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
17 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
27 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
37 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
46 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
56 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
71 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
81 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
91 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
220 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
[all …]
H A Davx2-vector-shifts.ll11 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
24 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
39 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
54 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
67 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
101 define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
116 define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
129 define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
144 define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
204 define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
[all …]
H A Dcombine-mul.ll464 define <4 x i64> @fuzz15429(<4 x i64> %InVec) {
483 %mul = mul <4 x i64> %InVec, <i64 1, i64 2, i64 4, i64 8>
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/X86/
H A Dx86-pshufb-inseltpoison.ll6 define <16 x i8> @identity_test(<16 x i8> %InVec) {
59 define <16 x i8> @splat_test(<16 x i8> %InVec) {
92 ; vector %InVec and a vector of all zeroes.
94 define <16 x i8> @blend1(<16 x i8> %InVec) {
103 define <16 x i8> @blend2(<16 x i8> %InVec) {
112 define <16 x i8> @blend3(<16 x i8> %InVec) {
121 define <16 x i8> @blend4(<16 x i8> %InVec) {
130 define <16 x i8> @blend5(<16 x i8> %InVec) {
139 define <16 x i8> @blend6(<16 x i8> %InVec) {
286 define <16 x i8> @permute1(<16 x i8> %InVec) {
[all …]
H A Dx86-pshufb.ll6 define <16 x i8> @identity_test(<16 x i8> %InVec) {
59 define <16 x i8> @splat_test(<16 x i8> %InVec) {
92 ; vector %InVec and a vector of all zeroes.
94 define <16 x i8> @blend1(<16 x i8> %InVec) {
103 define <16 x i8> @blend2(<16 x i8> %InVec) {
112 define <16 x i8> @blend3(<16 x i8> %InVec) {
121 define <16 x i8> @blend4(<16 x i8> %InVec) {
130 define <16 x i8> @blend5(<16 x i8> %InVec) {
139 define <16 x i8> @blend6(<16 x i8> %InVec) {
286 define <16 x i8> @permute1(<16 x i8> %InVec) {
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp526 static void concatSubVector(Value **Vec, ArrayRef<Instruction *> InVec, in concatSubVector() argument
530 Vec[i] = InVec[i]; in concatSubVector()
537 InVec[j * 6 + i], InVec[j * 6 + i + 3], makeArrayRef(Concat, 32)); in concatSubVector()
547 ArrayRef<Instruction *> InVec, SmallVectorImpl<Value *> &TransposedMatrix, in deinterleave8bitStride3() argument
573 concatSubVector(Vec, InVec, VecElems, Builder); in deinterleave8bitStride3()
630 ArrayRef<Instruction *> InVec, SmallVectorImpl<Value *> &TransposedMatrix, in interleave8bitStride3() argument
659 Vec[0] = Builder.CreateShuffleVector(InVec[0], VPAlign2); in interleave8bitStride3()
660 Vec[1] = Builder.CreateShuffleVector(InVec[1], VPAlign3); in interleave8bitStride3()
661 Vec[2] = InVec[2]; in interleave8bitStride3()
H A DX86ISelLowering.cpp54393 SDValue InVec = N->getOperand(0); in combineEXTRACT_SUBVECTOR() local
54395 SDValue InVecBC = peekThroughBitcasts(InVec); in combineEXTRACT_SUBVECTOR()
54396 EVT InVecVT = InVec.getValueType(); in combineEXTRACT_SUBVECTOR()
54436 if (InVec.getOpcode() == ISD::BUILD_VECTOR) in combineEXTRACT_SUBVECTOR()
54445 InVec.getOpcode() == ISD::INSERT_SUBVECTOR && InVec.hasOneUse() && in combineEXTRACT_SUBVECTOR()
54453 InVec.getOperand(1), in combineEXTRACT_SUBVECTOR()
54496 unsigned InOpcode = InVec.getOpcode(); in combineEXTRACT_SUBVECTOR()
54497 if (InVec.hasOneUse()) { in combineEXTRACT_SUBVECTOR()
54525 SDValue Ext = InVec.getOperand(0); in combineEXTRACT_SUBVECTOR()
54544 SDValue InVecSrc = InVec.getOperand(0); in combineEXTRACT_SUBVECTOR()
[all …]
/llvm-project-15.0.7/cross-project-tests/debuginfo-tests/dexter-tests/
H A Doptnone-vectors-and-functions.cpp90 T test3(T InVec) { in test3() argument
93 result[i] = InVec[i]; // DexLabel('break_6') in test3()
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp93 auto InVec = DAG->getConstant(0, Loc, InVecVT); in TEST_F() local
94 auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
106 auto InVec = DAG->getConstant(0, Loc, InVecVT); in TEST_F() local
107 auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
136 auto InVec = DAG->getConstant(1, Loc, InVecVT); in TEST_F() local
137 auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
148 auto InVec = DAG->getConstant(1, Loc, InVecVT); in TEST_F() local
149 auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1746 SDValue InVec = N->getOperand(0); in PerformDAGCombine() local
1752 return InVec; in PerformDAGCombine()
1754 EVT VT = InVec.getValueType(); in PerformDAGCombine()
1769 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1770 Ops.append(InVec.getNode()->op_begin(), in PerformDAGCombine()
1771 InVec.getNode()->op_end()); in PerformDAGCombine()
1772 } else if (InVec.isUndef()) { in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp3432 SDValue InVec = N->getOperand(OpNo); in SplitVecOp_TruncateHelper() local
3433 EVT InVT = InVec->getValueType(0); in SplitVecOp_TruncateHelper()
3464 GetSplitVector(InVec, InLoVec, InHiVec); in SplitVecOp_TruncateHelper()
4328 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops); in WidenVecRes_Convert() local
4330 return DAG.getNode(Opcode, DL, WidenVT, InVec); in WidenVecRes_Convert()
4331 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags); in WidenVecRes_Convert()
5798 SDValue InVec = N->getOperand(0); in WidenVecOp_INSERT_SUBVECTOR() local
5803 if (SubVec.getValueType().knownBitsLE(VT) && InVec.isUndef() && in WidenVecOp_INSERT_SUBVECTOR()
5805 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, InVec, SubVec, in WidenVecOp_INSERT_SUBVECTOR()
H A DSelectionDAG.cpp3627 SDValue InVec = Op.getOperand(0); in computeKnownBits() local
3629 EVT VecVT = InVec.getValueType(); in computeKnownBits()
3649 Known = computeKnownBits(InVec, DemandedSrcElts, Depth + 1); in computeKnownBits()
3658 SDValue InVec = Op.getOperand(0); in computeKnownBits() local
3676 Known2 = computeKnownBits(InVec, DemandedVecElts, Depth + 1); in computeKnownBits()
4303 SDValue InVec = Op.getOperand(0); in ComputeNumSignBits() local
4323 Tmp2 = ComputeNumSignBits(InVec, DemandedVecElts, Depth + 1); in ComputeNumSignBits()
4330 SDValue InVec = Op.getOperand(0); in ComputeNumSignBits() local
4332 EVT VecVT = InVec.getValueType(); in ComputeNumSignBits()
4354 return ComputeNumSignBits(InVec, DemandedSrcElts, Depth + 1); in ComputeNumSignBits()
H A DDAGCombiner.cpp19498 SDValue InVec = N->getOperand(0); in visitINSERT_VECTOR_ELT() local
19503 EVT VT = InVec.getValueType(); in visitINSERT_VECTOR_ELT()
19515 return InVec; in visitINSERT_VECTOR_ELT()
19557 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
19558 && isa<ConstantSDNode>(InVec.getOperand(2))) { in visitINSERT_VECTOR_ELT()
19559 unsigned OtherElt = InVec.getConstantOperandVal(2); in visitINSERT_VECTOR_ELT()
19566 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2)); in visitINSERT_VECTOR_ELT()
19606 for (SDValue CurVec = InVec; CurVec;) { in visitINSERT_VECTOR_ELT()
23101 SDValue InVec = InVal->getOperand(0); in visitSCALAR_TO_VECTOR() local
23103 auto InVecT = InVec.getValueType(); in visitSCALAR_TO_VECTOR()
[all …]
H A DSelectionDAGBuilder.cpp3538 SDValue InVec = getValue(I.getOperand(0)); in visitInsertElement() local
3544 InVec, InVal, InIdx)); in visitInsertElement()
3549 SDValue InVec = getValue(I.getOperand(0)); in visitExtractElement() local
3554 InVec, InIdx)); in visitExtractElement()
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp8026 Value *InVec = vectorizeTree(E->getOperand(0)); in vectorizeTree() local
8034 Value *V = Builder.CreateCast(CI->getOpcode(), InVec, VecTy); in vectorizeTree()