Searched refs:In0 (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanRecipes.cpp | 786 Value *In0 = State.get(getIncomingValue(In), Part); in execute() local
788 Entry[Part] = In0; // Initialize with the first incoming value. in execute()
794 State.Builder.CreateSelect(Cond, In0, Entry[Part], "predphi"); in execute()
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| H A D | LoopVectorizationLegality.cpp | 1033 Value *In0 = const_cast<Value *>(V); in isInductionPhi() local
1034 PHINode *PN = dyn_cast_or_null<PHINode>(In0); in isInductionPhi()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 53440 SDValue In0, In1; in matchPMADDWD_2() local
53477 if (!In0) { in matchPMADDWD_2()
53478 In0 = N00In; in matchPMADDWD_2()
53483 if (In0.getValueSizeInBits() < VT.getSizeInBits() || in matchPMADDWD_2()
53489 if (In0 != N00In) in matchPMADDWD_2()
53491 if (In0 != N10In) in matchPMADDWD_2()
53493 if (In0 != N00In || In1 != N01In || In0 != N10In || In1 != N11In) in matchPMADDWD_2()
53512 if (OutVT16.bitsLT(In0.getValueType())) { in matchPMADDWD_2()
53513 In0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT16, In0, in matchPMADDWD_2()
53520 return SplitOpsAndApply(DAG, Subtarget, DL, VT, { In0, In1 }, in matchPMADDWD_2()
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | LangRef.rst | 9489 | In0 | In1 | Out |
9540 | In0 | In1 | Out |
9592 | In0 | In1 | Out |
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