| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 2212 Register ImmReg = createResultReg(&PPC::CRBITRCRegClass); in PPCMaterializeInt() local
2214 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg); in PPCMaterializeInt()
2215 return ImmReg; in PPCMaterializeInt()
2232 Register ImmReg = createResultReg(RC); in PPCMaterializeInt() local
2233 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg) in PPCMaterializeInt()
2235 return ImmReg; in PPCMaterializeInt()
2394 Register ImmReg = createResultReg(&PPC::CRBITRCRegClass); in fastEmit_i() local
2396 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg); in fastEmit_i()
2397 return ImmReg; in fastEmit_i()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 2011 unsigned ImmReg = R600::ALU_LITERAL_X; in FoldOperand() local
2018 ImmReg = R600::ZERO; in FoldOperand()
2020 ImmReg = R600::HALF; in FoldOperand()
2022 ImmReg = R600::ONE; in FoldOperand()
2030 ImmReg = R600::ZERO; in FoldOperand()
2032 ImmReg = R600::ONE_INT; in FoldOperand()
2041 if (ImmReg == R600::ALU_LITERAL_X) { in FoldOperand()
2049 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()
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| H A D | SILoadStoreOptimizer.cpp | 1124 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeRead2Pair() local
1125 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
1132 .addReg(ImmReg) in mergeRead2Pair()
1216 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeWrite2Pair() local
1217 BuildMI(*MBB, InsertBefore, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
1224 .addReg(ImmReg) in mergeWrite2Pair()
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| H A D | SIInstrInfo.cpp | 7087 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
7092 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
7096 .addReg(ImmReg, RegState::Kill) in movePackToVALU()
7106 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
7107 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
7110 .addReg(ImmReg, RegState::Kill) in movePackToVALU()
7127 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
7132 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
7136 .addReg(ImmReg, RegState::Kill) in movePackToVALU()
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| H A D | AMDGPUInstructionSelector.cpp | 1984 Register ImmReg = MRI->createVirtualRegister(DstRC); in selectG_TRUNC() local
1999 BuildMI(*MBB, I, DL, TII.get(MovOpc), ImmReg) in selectG_TRUNC()
2003 .addReg(ImmReg); in selectG_TRUNC()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 464 Register ImmReg = createResultReg(RC); in ARMMaterializeInt() local
466 TII.get(Opc), ImmReg) in ARMMaterializeInt()
468 return ImmReg; in ARMMaterializeInt()
480 Register ImmReg = createResultReg(RC); in ARMMaterializeInt() local
482 TII.get(Opc), ImmReg) in ARMMaterializeInt()
484 return ImmReg; in ARMMaterializeInt()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4601 unsigned ImmReg = DstReg; in expandSgeImm() local
4606 ImmReg = ATReg; in expandSgeImm()
4613 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI); in expandSgeImm()
4631 unsigned ImmReg = DstReg; in expandSgtImm() local
4654 ImmReg = ATReg; in expandSgtImm()
4657 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSgtImm()
4662 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSgtImm()
4731 unsigned ImmReg = DstReg; in expandSleImm() local
4736 ImmReg = ATReg; in expandSleImm()
4739 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSleImm()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1516 Register ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL); in processBlock() local
1517 if (ImmReg) { in processBlock()
1518 HBS::replaceReg(DR, ImmReg, MRI); in processBlock()
1519 BT.put(ImmReg, DRC); in processBlock()
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