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/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h125 assert((Imm & 0x7) == Imm && "invalid immediate!"); in getExtendType()
216 if (Imm == 0ULL || Imm == ~0ULL || in processLogicalImmediate()
228 if ((Imm & Mask) != ((Imm >> Size) & Mask)) { in processLogicalImmediate()
453 return ((Imm >> 32) == (Imm & 0xffffffffULL)) && in isAdvSIMDModImmType1()
468 return ((Imm >> 32) == (Imm & 0xffffffffULL)) && in isAdvSIMDModImmType2()
483 return ((Imm >> 32) == (Imm & 0xffffffffULL)) && in isAdvSIMDModImmType3()
577 ((Imm >> 56) == (Imm & 0x000000ffULL)); in isAdvSIMDModImmType9()
768 if ((Imm & Mask) != 0 && (Imm & Mask) != Mask) in isSVECpyImm()
774 return int8_t(Imm) == T(Imm); in isSVECpyImm()
779 return int16_t(Imm) == T(Imm); in isSVECpyImm()
[all …]
/llvm-project-15.0.7/llvm/test/ObjectYAML/MachO/
H A Dlazy_bind_opcode.yaml66 Imm: 2
70 Imm: 1
72 Imm: 0
75 Imm: 0
77 Imm: 0
79 Imm: 2
83 Imm: 1
85 Imm: 0
88 Imm: 0
90 Imm: 0
[all …]
H A Dbind_opcode.yaml66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
H A Dweak_bind_opcode.yaml66 Imm: 1
68 Imm: 0
71 Imm: 1
73 Imm: 2
77 Imm: 0
79 Imm: 0
82 Imm: 0
84 Imm: 0
87 Imm: 0
89 Imm: 2
[all …]
H A Dout_of_order_linkedit.yaml144 Imm: 1
146 Imm: 2
150 Imm: 0
154 Imm: 0
157 Imm: 1
160 Imm: 0
163 Imm: 1
166 Imm: 2
171 Imm: 0
174 Imm: 0
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h120 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } in getSOImmValImm() argument
123 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } in getSOImmValRot() argument
147 if (Imm & 63U) { in getSOImmValRotate()
277 unsigned u, Vs, Imm; in getT2SOImmValSplatVal() local
285 Imm = Vs & 0xff; in getT2SOImmValSplatVal()
287 u = Imm | (Imm << 16); in getT2SOImmValSplatVal()
342 unsigned V = Imm; in isT2SOImmTwoPartVal()
356 V = Imm; in isT2SOImmTwoPartVal()
372 unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm; in getT2SOImmTwoPartFirst()
387 Imm ^= getT2SOImmTwoPartFirst(Imm); in getT2SOImmTwoPartSecond()
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-lipo/Inputs/
H A Darmv7-slice-big.yaml389 Imm: 1
391 Imm: 2
397 Imm: 2
399 Imm: 0
403 Imm: 2
405 Imm: 2
407 Imm: 0
414 Imm: 0
417 Imm: 3
420 Imm: 0
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
46 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL()
66 if (!(Imm & 0xffff)) { in GetInstSeqLs()
67 GetInstSeqLsSLL(Imm, RemSize, SeqLs); in GetInstSeqLs()
71 GetInstSeqLsADDiu(Imm, RemSize, SeqLs); in GetInstSeqLs()
75 if (Imm & 0x8000) { in GetInstSeqLs()
77 GetInstSeqLsORi(Imm, RemSize, SeqLsORi); in GetInstSeqLs()
148 if (LastInstrIsADDiu | !Imm) in Analyze()
149 GetInstSeqLsADDiu(Imm, Size, SeqLs); in Analyze()
[all …]
H A DMipsISelDAGToDAG.h98 virtual bool selectVSplat(SDNode *N, APInt &Imm,
101 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
103 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
105 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
107 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
109 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
111 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
113 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
115 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
123 virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const;
[all …]
H A DMipsSEISelDAGToDAG.h96 bool selectVSplat(SDNode *N, APInt &Imm,
99 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
102 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
104 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
106 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
108 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
110 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
112 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
114 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
116 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
[all …]
/llvm-project-15.0.7/llvm/test/MC/Lanai/
H A Dmemory.s12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
28 ! CHECK-NEXT: <MCOperand Imm:0>
29 ! CHECK-NEXT: <MCOperand Imm:0>
36 ! CHECK-NEXT: <MCOperand Imm:291>
44 ! CHECK-NEXT: <MCOperand Imm:-4>
53 ! CHECK-NEXT: <MCOperand Imm:0>
76 ! CHECK-NEXT: <MCOperand Imm:4>
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp74 if (isInt<16>(Imm) || isUInt<16>(Imm)) in printU16ImmOperand()
127 if (Imm != 0) { in printOffset()
137 if (Imm != 0) { in printFlatOffset()
545 assert(isUInt<32>(Imm) || isInt<32>(Imm)); in printImmediate64()
557 if (!Imm) in printBLGP()
579 if (!Imm) in printCBSZ()
589 if (!Imm) in printABID()
1009 if (Imm) { in printBoundCtrl()
1019 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) { in printFI()
1029 switch (Imm) { in printSDWASel()
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmacro-aliases.s7 # CHECK: Imm:-4
9 # CHECK: Imm:-4
11 # CHECK: Imm:-4
13 # CHECK: Imm:4
15 # CHECK: Imm:4
17 # CHECK: Imm:4
19 # CHECK: Imm:8
22 # CHECK: Imm:-8
28 # CHECK: Imm:8
30 # CHECK: Imm:8
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp220 if (Imm != 0) in decodeImmZeroOperand()
241 uint64_t Base = Imm >> 16; in decodeMemRIOperands()
277 uint64_t Base = Imm >> 14; in decodeMemRIXOperands()
316 uint64_t Base = Imm >> 12; in decodeMemRIX16Operands()
331 uint64_t Base = Imm >> 34; in decodeMemRI34PCRelOperands()
345 uint64_t Base = Imm >> 34; in decodeMemRI34Operands()
361 uint64_t Base = Imm >> 5; in decodeSPE8Operands()
362 uint64_t Disp = Imm & 0x1F; in decodeSPE8Operands()
377 uint64_t Base = Imm >> 5; in decodeSPE4Operands()
378 uint64_t Disp = Imm & 0x1F; in decodeSPE4Operands()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp171 if (!isUInt<N>(Imm)) in decodeUImmOperand()
179 if (!isUInt<N>(Imm)) in decodeSImmOperand()
188 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
194 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand()
200 return decodeUImmOperand<3>(Inst, Imm); in decodeU3ImmOperand()
206 return decodeUImmOperand<4>(Inst, Imm); in decodeU4ImmOperand()
212 return decodeUImmOperand<6>(Inst, Imm); in decodeU6ImmOperand()
218 return decodeUImmOperand<8>(Inst, Imm); in decodeU8ImmOperand()
224 return decodeUImmOperand<12>(Inst, Imm); in decodeU12ImmOperand()
230 return decodeUImmOperand<16>(Inst, Imm); in decodeU16ImmOperand()
[all …]
/llvm-project-15.0.7/lld/test/MachO/
H A Dbind-opcodes.s17 # CHECK-NEXT: Imm: 0
20 # CHECK-NEXT: Imm: 1
23 # CHECK-NEXT: Imm: 2
26 # CHECK-NEXT: Imm: 2
30 # CHECK-NEXT: Imm: 0
34 # CHECK-NEXT: Imm: 0
38 # CHECK-NEXT: Imm: 0
42 # CHECK-NEXT: Imm: 0
46 # CHECK-NEXT: Imm: 0
49 # CHECK-NEXT: Imm: 0
[all …]
H A Drebase-opcodes.s14 # CHECK-NEXT: Imm: 1
16 # CHECK-NEXT: Imm: 1
23 # CHECK-NEXT: Imm: 0
31 # CHECK-NEXT: Imm: 3
36 # CHECK-NEXT: Imm: 15
44 # CHECK-NEXT: Imm: 0
51 # CHECK-NEXT: Imm: 0
57 # CHECK-NEXT: Imm: 2
62 # CHECK-NEXT: Imm: 0
71 # CHECK-NEXT: Imm: 0
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ExpandImm.cpp25 return (Imm >> (ChunkIdx * 16)) & 0xFFFF; in getChunk()
129 Imm &= ~(Mask << (Idx * 16)); in updateImm()
132 Imm |= Mask << (Idx * 16); in updateImm()
134 return Imm; in updateImm()
258 Imm = ~Imm; in expandMOVImmSimple()
263 Imm &= (1LL << 32) - 1; in expandMOVImmSimple()
270 if (Imm != 0) { in expandMOVImmSimple()
271 unsigned LZ = countLeadingZeros(Imm); in expandMOVImmSimple()
276 unsigned Imm16 = (Imm >> Shift) & Mask; in expandMOVImmSimple()
287 Imm = ~Imm; in expandMOVImmSimple()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXInstPrinter.cpp101 int64_t Imm = MO.getImm(); in printCvtMode() local
105 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode()
109 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode()
113 if (Imm & NVPTX::PTXCvtMode::RELU_FLAG) in printCvtMode()
158 int64_t Imm = MO.getImm(); in printCmpMode() local
162 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) in printCmpMode()
232 int Imm = (int) MO.getImm(); in printLdStCode() local
234 if (Imm) in printLdStCode()
237 switch (Imm) { in printLdStCode()
283 int Imm = (int)MO.getImm(); in printMmaCode() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.h31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 void DecodePSLLDQMask(unsigned NumElts, unsigned Imm,
55 void DecodePSRLDQMask(unsigned NumElts, unsigned Imm,
58 void DecodePALIGNRMask(unsigned NumElts, unsigned Imm,
61 void DecodeVALIGNMask(unsigned NumElts, unsigned Imm,
65 void DecodePSHUFMask(unsigned NumElts, unsigned ScalarBits, unsigned Imm,
69 void DecodePSHUFHWMask(unsigned NumElts, unsigned Imm,
73 void DecodePSHUFLWMask(unsigned NumElts, unsigned Imm,
104 void DecodeBLENDMask(unsigned NumElts, unsigned Imm,
107 void DecodeVPERM2X128Mask(unsigned NumElts, unsigned Imm,
[all …]
H A DX86ShuffleDecode.cpp34 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask()
35 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask()
36 unsigned CountS = (Imm >> 6) & 3; in DecodeINSERTPSMask()
106 if (i >= Imm) M = i - Imm + l; in DecodePSLLDQMask()
117 unsigned Base = i + Imm; in DecodePSRLDQMask()
130 unsigned Base = i + Imm; in DecodePALIGNRMask()
142 Imm = Imm & (NumElts - 1); in DecodeVALIGNMask()
144 ShuffleMask.push_back(i + Imm); in DecodeVALIGNMask()
166 unsigned NewImm = Imm; in DecodePSHUFHWMask()
180 unsigned NewImm = Imm; in DecodePSHUFLWMask()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp309 ImmOp Imm; member
327 Imm = o.Imm; in RISCVOperand()
382 int64_t Imm; in isBareSimmNLsb0() local
398 int64_t Imm; in isBareSymbol() local
520 (isRV64() || (isInt<32>(Imm) || isUInt<32>(Imm))); in isImmXLenLI()
531 return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm); in isUImmLog2XLen()
544 return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm); in isUImmLog2XLenNonZero()
555 return (isRV64() && isUInt<5>(Imm)) || isUInt<4>(Imm); in isUImmLog2XLenHalf()
606 return IsConstantImm && isInt<6>(Imm) && (Imm != 0) && in isSImm6NonZero()
617 (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)) && in isCLUIImm()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp247 if ((Imm >> 7) & 0x1) { in decodeLRW16Imm8()
262 if (Imm == 0) in decodeJMPIXImmOperand()
264 else if (Imm == 1) in decodeJMPIXImmOperand()
266 else if (Imm == 2) in decodeJMPIXImmOperand()
268 else if (Imm == 3) in decodeJMPIXImmOperand()
281 auto Imm5 = Imm & 0x1f; in DecodeRegSeqOperand()
282 auto Ry = (Imm >> 5) & 0x1f; in DecodeRegSeqOperand()
298 auto Imm5 = Imm & 0x1f; in DecodeRegSeqOperandF1()
315 auto Imm5 = Imm & 0x1f; in DecodeRegSeqOperandD1()
332 auto Imm5 = Imm & 0x1f; in DecodeRegSeqOperandF2()
[all …]
/llvm-project-15.0.7/lldb/test/API/functionalities/disassemble/aarch64-adrp-add/
H A Da.out-arm64.yaml260 Imm: 1
262 Imm: 3
265 Imm: 1
267 Imm: 0
270 Imm: 1
273 Imm: 0
276 Imm: 1
279 Imm: 2
283 Imm: 0
286 Imm: 0
[all …]
/llvm-project-15.0.7/lldb/test/Shell/ObjectFile/MachO/
H A Dsymtab.yaml319 Imm: 1
321 Imm: 3
325 Imm: 3
327 Imm: 0
330 Imm: 2
333 Imm: 0
336 Imm: 1
339 Imm: 2
344 Imm: 0
347 Imm: 0
[all …]

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