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/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dfor-loop-peeling.mlir16 // CHECK: %[[RESULT:.*]] = scf.for %[[IV2:.*]] = %[[NEW_UB]] to %[[UB]]
18 // CHECK: %[[REM:.*]] = affine.apply #[[MAP1]](%[[IV2]])[%[[UB]]]
84 // CHECK: %[[RESULT:.*]] = scf.for %[[IV2:.*]] = %[[NEW_UB]] to %[[UB]]
86 // CHECK: %[[REM:.*]] = affine.apply #[[MAP1]](%[[IV2]])[%[[UB]]]
122 // CHECK: scf.for %[[IV2:.*]] = %[[NEW_UB]] to %[[UB]] step %[[C4]] {
123 // CHECK: %[[REM:.*]] = affine.apply #[[MAP1]](%[[IV2]])[%[[UB]]]
176 // CHECK: scf.for %[[IV2:.*]] = {{.*}} to %[[UB]] step %[[STEP]] {
177 // CHECK: %[[RES_IF_0:.*]] = affine.apply #[[MAP5]](%[[IV2]])[%[[UB]]]
179 // CHECK: %[[RES_IF_1:.*]] = affine.apply #[[MAP6]](%[[IV2]])[%[[UB]]]
181 // CHECK: %[[RES_IF_2:.*]] = affine.apply #[[MAP6]](%[[IV2]])[%[[UB]]]
[all …]
H A Dloop-pipelining.mlir94 // CHECK-NEXT: %[[IV2:.*]] = arith.addi %[[IV]], %[[C2]] : index
95 // CHECK-NEXT: %[[L3:.*]] = memref.load %[[A]][%[[IV2]]] : memref<?xf32>
143 // NOEPILOGUE-NEXT: %[[IV2:.*]] = arith.addi %[[IV]], %[[C2]] : index
145 // NOEPILOGUE-NEXT: %[[PL:.*]] = memref.load %[[A]][%[[IV2]]] : memref<?xf32>
323 // CHECK-NEXT: %[[IV2:.*]] = arith.addi %[[IV]], %[[C2]] : index
324 // CHECK-NEXT: %[[L2:.*]] = memref.load %[[A]][%[[IV2]]] : memref<?xf32>
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Dlftr-pr31181.ll189 ; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV2_INC:%.*]], [[ALWAYS_TAKEN]] ]
193 ; CHECK-NEXT: store volatile i32 [[IV2]], i32* [[PTR]], align 4
197 ; CHECK-NEXT: [[IV2_INC]] = add nuw i32 [[IV2]], 1
234 ; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV2_INC:%.*]], [[ALWAYS_TAKEN]] ]
236 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2]], -2147483628
241 ; CHECK-NEXT: store volatile i32 [[IV2]], i32* [[PTR]], align 4
245 ; CHECK-NEXT: [[IV2_INC]] = add nuw i32 [[IV2]], 1
286 ; CHECK-NEXT: store volatile i32 [[IV2]], i32* [[PTR]], align 4
289 ; CHECK-NEXT: [[IV2_INC]] = add nuw nsw i32 [[IV2]], 1
329 ; CHECK-NEXT: store volatile i32 [[IV2]], i32* [[PTR]], align 4
[all …]
H A Dpr28705.ll26 ; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 1, [[FOR_BODY650_LR_PH]] ], [ [[INC_I_I]], [[FOR_BODY650]]…
27 …K-NEXT: [[ARRAYIDX_I_I1105:%.*]] = getelementptr inbounds i8, i8* [[REF_I1174:%.*]], i32 [[IV2]]
29 ; CHECK-NEXT: [[INC_I_I]] = add nuw nsw i32 [[IV2]], 1
H A Dlcssa-preservation.ll60 ; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[LOOP1]] ], [ 1, [[LOOP2]] ]
63 ; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi i64 [ [[IV2]], [[LOOP2]] ]
H A Drlev-add-me.ll89 ; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV2_NEXT:%.*]], [[WRONG_LOOP]] ]
90 ; CHECK-NEXT: [[IV2_NEXT]] = add i32 [[IV2]], 1
95 ; CHECK-NEXT: [[IV2_LCSSA:%.*]] = phi i32 [ [[IV2]], [[WRONG_LOOP]] ]
H A Dlftr-multi-exit.ll448 ; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, [[OUTER]] ], [ [[IV2_NEXT:%.*]], [[INNER_LATCH:%.*]] ]
449 ; CHECK-NEXT: store volatile i32 [[IV2]], i32* @A, align 4
450 ; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i32 [[IV2]], 1
451 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2]], 20
H A Dfinite-exit-comparisons.ll969 ; CHECK-NEXT: [[IV2:%.*]] = phi i16 [ [[ZEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
975 ; CHECK-NEXT: [[IV2_LCSSA:%.*]] = phi i16 [ [[IV2]], [[FOR_BODY]] ]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dtile-and-fuse-tensors.mlir120 // CHECK-NEXT: scf.for %[[IV2:.+]] = %{{.+}} to %{{.+}} step %{{.+}} iter_args(%[[ARG2:.+]] = %…
131 // CHECK: tensor.insert_slice %[[ADD]] into %[[ARG2]][0, %[[IV0]], %[[IV1]], %[[IV2]]] […
239 // CHECK-NEXT: scf.for %[[IV2:.+]] = %{{.+}} to %[[ELEM_OW]]
240 // CHECK-NEXT: %[[SIZE_ELEM_OW:.+]] = affine.min #[[BOUND4_MAP]](%[[IV2]])[%[[ELEM_OW]]]
241 // CHECK-NEXT: %[[SIZE_ELEM_OC:.+]] = affine.min #[[BOUND2_MAP]](%[[IV2]])[%[[ELEM_OC]]]
242 // CHECK-NEXT: %[[OFFSET_OW:.+]] = affine.apply #[[X2_MAP]](%[[IV2]])
246 // CHECK-NEXT: %[[SIZE_ELEM_OW_2:.+]] = affine.min #[[BOUND4_MAP_2]](%[[IV2]])[%[[FILL_W]],…
248 … %[[ST_ELEM:.+]] = tensor.extract_slice %[[ELEM]][%[[IV0]], %[[IV1]], %[[IV2]], %[[IV3]]]
250 // CHECK-NEXT: %[[ST_ARG:.+]] = tensor.extract_slice %[[ARG]][%[[IV0]], %[[IV1]], %[[IV2]…
255 … %[[ST_FILL:.+]] = tensor.extract_slice %[[FILL]][%[[IV0]], %[[IV1]], %[[IV2]], %[[IV3]]]
[all …]
H A Dparallel-loops.mlir58 // CHECK: scf.for %[[IV2:.*]] = %[[C0]] to %[[D2]] step %[[C1]]
60 // CHECK: memref.load %{{.*}}[%[[IV0]], %[[IV1]], %[[IV2]], %[[IV3]]]
93 // CHECK: scf.for %[[IV2:.*]] = %[[C0]] to %[[D2]] step %[[C1]]
96 // CHECK: memref.load %{{.*}}[%[[IV0]], %[[IV1]], %[[IV2]], %[[IV3]], %[[IV4]], %[[IV5]…
H A Dtransform-op-fuse.mlir73 // CHECK: scf.for %[[IV2:.+]] = %{{.+}} to %{{.+}} step %[[C4]] iter_args(%[[FOR_ARG2:.+]…
H A Dfuse-with-reshape-by-collapsing.mlir100 // CHECK: %[[IV2:.+]] = linalg.index 2
109 // CHECK: %[[T2:.+]] = arith.addi %[[T1]], %[[IV2]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/ARM/
H A Dloop-unrolling.ll16 ; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV2:%[a-z.0-9]+]], %for.body ]
18 ; CHECK-NOUNROLL: [[IV2]] = add nuw nsw i32 [[IV1]], 1
19 ; CHECK-NOUNROLL: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV2]], 1024
24 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
25 ; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
66 ; CHECK-NOUNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV2:%[a-z.0-9]+]], …
68 ; CHECK-NOUNROLL: [[IV2]] = add nuw i32 [[IV1]], 1
73 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
74 ; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
128 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopSimplify/
H A Dsingle-backedge.ll16 %IV = phi i32 [ 1, %0 ], [ %IV2, %BE1 ], [ %IV2, %BE2 ] ; <i32> [#uses=2]
18 %IV2 = add i32 %IV, 2, !dbg !8 ; <i32> [#uses=2]
/llvm-project-15.0.7/mlir/test/Interfaces/TilingInterface/
H A Dtile-using-interface.mlir72 // CHECK: scf.for %[[IV2:[a-zA-Z0-9]+]] = %[[C0]] to %[[K]] step %[[C30]]
73 // CHECK: %[[TS_K:.+]] = affine.min #[[MAP2]](%[[IV2]])[%[[C30]], %[[K]]]
75 // CHECK-SAME: [%[[IV0]], %[[IV2]]] [%[[TS_M]], %[[TS_K]]] [1, 1]
77 // CHECK-SAME: [%[[IV2]], %[[IV1]]] [%[[TS_K]], %[[TS_N]]] [1, 1]
178 // CHECK: scf.for %[[IV2:[a-zA-Z0-9]+]] = %[[C0]] to %[[C]] step %[[C30]]
180 // CHECK-DAG: %[[TS_C:.+]] = affine.min #[[MAP2]](%[[IV2]])[%[[C30]], %[[C]]]
184 // CHECK-SAME: [0, %[[IV0]], %[[IV1]], %[[IV2]]] [%[[N]], %[[TS_H]], %[[TS_W]], %[[TS_C…
262 // CHECK-DAG: %[[TS_M:.+]] = affine.min #[[MAP2]](%[[IV2]])[%[[C10]], %[[M]]]
264 // CHECK-SAME: [%[[IV2]], %[[IV1]]] [%[[TS_M]], %[[TS_K]]] [1, 1]
268 // CHECK-SAME: [%[[IV2]], %[[IV0]]] [%[[TS_M]], %[[TS_N]]] [1, 1]
[all …]
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dmatrix-type-operators.m20 // CHECK-NEXT: [[IV2:%.*]] = load %0*, %0** [[IV_ADDR]], align 8
21 // CHECK-NEXT: [[IV2_PTR:%.*]] = bitcast %0* [[IV2]] to i8*
47 // CHECK-NEXT: [[IV2:%.*]] = load %0*, %0** [[IV_ADDR]], align 8
48 // CHECK-NEXT: [[IV2_PTR:%.*]] = bitcast %0* [[IV2]] to i8*
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/X86/
H A Dexpander-crashes.ll27 ; CHECK-NEXT: [[IV2:%.*]] = phi %struct.hoge* [ [[IV2_NEXT:%.*]], [[LOOP_2_LATCH]] ], [ [[IV_NEX…
28 ; CHECK-NEXT: [[IV24:%.*]] = bitcast %struct.hoge* [[IV2]] to i32*
33 ; CHECK-NEXT: [[EC_2:%.*]] = icmp ugt %struct.hoge* [[IV2]], [[PTR_2:%.*]]
36 ; CHECK-NEXT: [[IV2_NEXT]] = getelementptr inbounds [[STRUCT_HOGE]], %struct.hoge* [[IV2]], i64 1
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Daffine-data-copy.mlir220 // CHECK-NEXT: affine.for %[[IV2:.*]] = #[[$MAP_IDENTITY]](%[[IV1]]) to min #[[$MAP_MIN_UB1]](%[[…
221 // CHECK-NEXT: affine.load %{{.*}}[%[[IV2]]] : memref<4096xf32>
222 // CHECK-NEXT: affine.store %{{.*}}, %[[BUF]][%[[IV2]] - %[[IV1]]] : memref<100xf32>
224 // CHECK-NEXT: affine.for %[[IV2:.*]] = #[[$MAP_IDENTITY]](%[[IV1]]) to min #[[$MAP_MIN_UB2]](%[[…
225 // CHECK-NEXT: affine.load %[[BUF]][-%[[IV1]] + %[[IV2]]] : memref<100xf32>
227 // CHECK-NEXT: affine.store %{{.*}}, %[[BUF]][-%[[IV1]] + %[[IV2]]] : memref<100xf32>
229 // CHECK: affine.for %[[IV2:.*]] = #[[$MAP_IDENTITY]](%[[IV1]]) to min #[[$MAP_MIN_UB1]](%[[…
230 // CHECK-NEXT: affine.load %[[BUF]][%[[IV2]] - %[[IV1]]] : memref<100xf32>
231 // CHECK-NEXT: affine.store %{{.*}}, %{{.*}}[%[[IV2]]] : memref<4096xf32>
H A Dunroll-jam.mlir290 // CHECK-NEXT: [[RES4:%[0-9]+]]:2 = affine.for [[IV2:%arg[0-9]+]] = 0 to 35 iter_args([[ACC3:%a…
291 // CHECK-NEXT: [[RES5:%[0-9]+]] = "bar"([[IV0]], [[IV1]], [[IV2]], [[ACC3]])
293 // CHECK-NEXT: [[RES6:%[0-9]+]] = "bar"([[INC1]], [[IV1]], [[IV2]], [[ACC4]])
344 // CHECK-NEXT: [[RES4:%[0-9]+]]:2 = affine.for [[IV2:%arg[0-9]+]] = 0 to 35 iter_args([[ACC3:%a…
345 // CHECK-NEXT: [[RES5:%[0-9]+]] = "bar"([[IV0]], [[IV1]], [[IV2]], [[ACC3]])
347 // CHECK-NEXT: [[RES6:%[0-9]+]] = "bar"([[INC1]], [[IV1]], [[IV2]], [[ACC4]])
409 // CHECK-NEXT: [[RES4:%[0-9]+]]:2 = affine.for [[IV2:%arg[0-9]+]] = 0 to 35 iter_args([[ACC7:%a…
410 // CHECK-NEXT: [[RES5:%[0-9]+]] = "bar"([[IV0]], [[IV1]], [[IV2]], [[ACC7]])
412 // CHECK-NEXT: [[RES6:%[0-9]+]] = "bar"([[INC1]], [[IV1]], [[IV2]], [[ACC8]])
478 // CHECK-NEXT: [[RES2:%[0-9]+]] = affine.for %[[IV2:arg[0-9]+]] = 0 to 30 iter_args([[ACC4:%arg[0-9…
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/Power/
H A Dincomplete-phi.ll19 ; CHECK: One incomplete PHI is found: %[[IV2:.*]] = phi [0 x %0]*
21 ; CHECK-NOT: Original iv: %[[IV2]]
22 ; CHECK-NOT: Eliminated congruent iv: %[[IV2]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopSimplifyCFG/
H A Dscev.ll20 ; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, %[[EXIT]] ], [ [[INC2:%.*]], %[[LOOP_BODY2]] ]
21 ; CHECK-NEXT: [[INC2]] = add i32 [[IV2]], 1
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dlvi-after-jumpthreading.ll65 ; IS________OPM-NEXT: [[IV2:%.*]] = phi i32 [ [[N]], [[ENTRY]] ], [ [[IV2_NEXT:%.*]], [[BACKEDGE…
67 ; IS________OPM-NEXT: [[CND2:%.*]] = icmp sgt i32 [[IV2]], 0
72 ; IS________OPM-NEXT: [[IV2_NEXT]] = sub nsw i32 [[IV2]], 1
87 ; IS________NPM-NEXT: [[IV2:%.*]] = phi i32 [ [[N]], [[ENTRY]] ], [ [[IV2_NEXT:%.*]], [[BACKEDGE…
89 ; IS________NPM-NEXT: [[CND2:%.*]] = icmp sgt i32 [[IV2]], 0
94 ; IS________NPM-NEXT: [[IV2_NEXT]] = sub nsw i32 [[IV2]], 1
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dreduction-odd-interleave-counts.ll12 ; UF3-NEXT: [[IV2:%.+]] = add i64 [[IV]], 8
15 ; UF3-NEXT: [[GEP2:%.+]] = getelementptr inbounds i32, i32* %A, i64 [[IV2]]
47 ; UF5-NEXT: [[IV2:%.+]] = add i64 [[IV]], 8
52 ; UF5-NEXT: [[GEP2:%.+]] = getelementptr inbounds i32, i32* %A, i64 [[IV2]]
H A Dinterleaved-accesses.ll1562 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV2:%.*]], [[LOOP]]…
1567 ; CHECK-NEXT: [[IV2]] = add nuw nsw i64 [[IV]], 2
1571 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i16, i16* [[A]], i64 [[IV2]]
/llvm-project-15.0.7/mlir/test/Dialect/Affine/SuperVectorize/
H A Dvectorize_1d.mlir196 // CHECK: affine.for %[[IV2:[arg0-9]+]] = 0 to 2 {
197 // CHECK-NEXT: %[[BROADCAST2:.*]] = vector.broadcast %[[IV2]] : index to vector<128xindex>
198 // CHECK-NEXT: %[[INDEX1:.*]] = affine.apply #[[$map0]](%[[IV0]], %[[IV2]], %[[IV1]])
199 // CHECK-NEXT: %[[INDEX2:.*]] = affine.apply #[[$map1]](%[[IV0]], %[[IV2]], %[[IV1]])

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