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/llvm-project-15.0.7/llvm/test/Transforms/ConstraintElimination/
H A Dloops-bottom-tested-base.ll14 ; CHECK-NEXT: [[T_2:%.*]] = icmp sge i32 [[IV]], 0
16 ; CHECK-NEXT: [[T_3:%.*]] = icmp sge i32 [[IV]], -1
18 ; CHECK-NEXT: [[C_1:%.*]] = icmp ult i32 [[IV]], [[N]]
20 ; CHECK-NEXT: [[C_2:%.*]] = icmp ugt i32 [[IV]], 1
23 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
59 ; CHECK-NEXT: [[T_1:%.*]] = icmp ule i32 [[IV]], 2
61 ; CHECK-NEXT: [[T_2:%.*]] = icmp sge i32 [[IV]], 0
63 ; CHECK-NEXT: [[T_3:%.*]] = icmp sge i32 [[IV]], -1
65 ; CHECK-NEXT: [[C_1:%.*]] = icmp ult i32 [[IV]], 2
67 ; CHECK-NEXT: [[C_2:%.*]] = icmp ugt i32 [[IV]], 1
[all …]
H A Dloops-header-tested-pointer-iv.ll13 ; CHECK-NEXT: [[C_2:%.*]] = icmp ule i8* [[IV]], [[END]]
15 ; CHECK-NEXT: [[T_2:%.*]] = icmp uge i8* [[IV]], [[START]]
17 ; CHECK-NEXT: [[C_1:%.*]] = icmp ule i8* [[IV]], [[END]]
20 ; CHECK-NEXT: [[T_1:%.*]] = icmp ult i8* [[IV]], [[UPPER]]
22 ; CHECK-NEXT: [[IV_NEXT]] = getelementptr inbounds i8, i8* [[IV]], i8 1
60 ; CHECK-NEXT: [[C_1:%.*]] = icmp ule i8* [[IV]], [[END]]
62 ; CHECK-NEXT: [[C_2:%.*]] = icmp uge i8* [[IV]], null
64 ; CHECK-NEXT: [[C_3:%.*]] = icmp ule i8* [[IV]], [[END]]
67 ; CHECK-NEXT: [[C_4:%.*]] = icmp ult i8* [[IV]], [[UPPER]]
69 ; CHECK-NEXT: [[IV_NEXT]] = getelementptr inbounds i8, i8* [[IV]], i8 1
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/Lint/
H A Dget-active-lane-mask.ll3 define <4 x i1> @t1(i32 %IV) {
6 ; CHECK-NEXT: %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0)
8 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0)
12 define <4 x i1> @t2(i32 %IV) {
17 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 1)
21 define <4 x i1> @t3(i32 %IV) {
26 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 -1)
30 define <4 x i1> @t4(i32 %IV, i32 %TC) {
35 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 %TC)
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Dlftr-multi-exit.ll21 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
22 ; CHECK-NEXT: store i32 [[IV]], i32* @A, align 4
57 ; CHECK-NEXT: store i32 [[IV]], i32* @A, align 4
175 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
176 ; CHECK-NEXT: store i32 [[IV]], i32* @A, align 4
211 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
250 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
278 ;; one IV when exit tests involve multiple IVs).
315 ; We can remove the decrementing IV entirely
402 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
[all …]
H A Dtrivial-checks.ll16 ; CHECK-NEXT: [[TMP:%.*]] = add i32 [[IV]], 1
20 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], -1
21 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 0
61 ; CHECK-NEXT: [[TMP:%.*]] = add i32 [[IV]], 1
65 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], -1
66 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 0
106 ; CHECK-NEXT: [[TMP:%.*]] = add i32 [[IV]], 1
110 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], -1
111 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 0
152 ; CHECK-NEXT: [[TMP:%.*]] = add i32 [[IV]], 1
[all …]
H A Dmonotonic_checks.ll14 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], -1
17 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ne i32 [[IV]], 0
53 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], -1
57 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ne i32 [[IV]], 1
94 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
97 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ne i32 [[IV]], 0
133 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
137 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ne i32 [[IV]], -2
172 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
210 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], -1
[all …]
H A Dcanonicalize-cmp.ll14 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_BE:%.*]] ]
15 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[IV]], 100
18 ; CHECK-NEXT: store i32 [[IV]], i32* [[P:%.*]], align 4
24 ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IV]], 100
27 ; CHECK-NEXT: store i32 [[IV]], i32* [[P]], align 4
33 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
83 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 100, [[IV]]
86 ; CHECK-NEXT: store i32 [[IV]], i32* [[P:%.*]], align 4
92 ; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i32 100, [[IV]]
95 ; CHECK-NEXT: store i32 [[IV]], i32* [[P]], align 4
[all …]
H A Dfinite-exit-comparisons.ll17 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
45 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
75 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
106 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
224 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
253 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
282 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
314 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
341 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
368 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DVPlanTransforms.cpp301 auto *IV = dyn_cast<VPWidenIntOrFpInductionRecipe>(&Phi); in removeRedundantInductionCasts() local
302 if (!IV || IV->getTruncInst()) in removeRedundantInductionCasts()
314 VPValue *FindMyCast = IV; in removeRedundantInductionCasts()
327 FindMyCast->replaceAllUsesWith(IV); in removeRedundantInductionCasts()
386 auto *IV = dyn_cast<VPWidenIntOrFpInductionRecipe>(&Phi); in optimizeInductions() local
387 if (!IV) in optimizeInductions()
390 none_of(IV->users(), [IV](VPUser *U) { return U->usesScalars(IV); })) in optimizeInductions()
396 Instruction *TruncI = IV->getTruncInst(); in optimizeInductions()
404 SetVector<VPUser *> Users(IV->user_begin(), IV->user_end()); in optimizeInductions()
406 if (HasOnlyVectorVFs && !U->usesScalars(IV)) in optimizeInductions()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopBoundSplit/
H A Dloop-bound-split.ll23 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1
80 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1
150 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IV]], 10
161 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1
235 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1
289 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1
363 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1
418 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1
492 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 2
547 ; CHECK-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 2
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/X86/
H A Deliminate-trunc.ll15 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
16 ; CHECK-NEXT: [[NARROW_IV:%.*]] = trunc i64 [[IV]] to i32
45 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
74 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
125 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
153 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
202 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
229 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
257 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
306 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/ARM/
H A Dinstr-size-costs.ll10 ; CHECK-V8-NEXT: [[ADDR_A:%.*]] = getelementptr i32, i32* [[A:%.*]], i32 [[IV]]
11 ; CHECK-V8-NEXT: [[ADDR_B:%.*]] = getelementptr i32, i32* [[B:%.*]], i32 [[IV]]
15 ; CHECK-V8-NEXT: [[ADDR_C:%.*]] = getelementptr i32, i32* [[C:%.*]], i32 [[IV]]
17 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
64 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
111 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
158 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
208 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
264 ; CHECK-V8-NEXT: [[COUNT:%.*]] = add nuw nsw i32 [[IV]], 1
320 ; CHECK-V8-NEXT: [[COUNT]] = add nuw i32 [[IV]], 1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LICM/
H A Dexplicit_guards.ll15 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[GUARDED:%.*]] ]
16 ; CHECK-NEXT: [[GUARD_COND:%.*]] = icmp slt i32 [[IV]], [[N:%.*]]
23 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV]], [[M:%.*]]
24 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
50 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[GUARDED:%.*]] ]
51 ; CHECK-NEXT: [[GUARD_COND:%.*]] = icmp slt i32 [[IV]], [[N:%.*]]
59 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV]], [[M:%.*]]
60 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
90 ; CHECK-NEXT: [[GUARD_COND:%.*]] = icmp slt i32 [[IV]], [[N]]
97 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV]], [[M:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopIdiom/X86/
H A Dlogical-right-shift-until-zero.ll29 ; CHECK-NEXT: [[IV_NEXT:%.*]] = add i8 [[IV]], 1
190 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
238 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
286 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
342 ; CHECK-NEXT: call void @escape_inner(i8 [[IV]], i8 [[IV]], i8 [[VAL_SHIFTED]], i1 [[LOOP_IVCHEC…
446 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 2
552 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
600 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
1047 ; IV must really be a PHI
1053 ; CHECK-NEXT: [[IV:%.*]] = add i8 0, 0
[all …]
H A Dleft-shift-until-zero.ll29 ; CHECK-NEXT: [[IV_NEXT:%.*]] = add i8 [[IV]], 1
190 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
238 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
286 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
342 ; CHECK-NEXT: call void @escape_inner(i8 [[IV]], i8 [[IV]], i8 [[VAL_SHIFTED]], i1 [[LOOP_IVCHEC…
446 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 2
552 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
600 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
1047 ; IV must really be a PHI
1053 ; CHECK-NEXT: [[IV:%.*]] = add i8 0, 0
[all …]
H A Darithmetic-right-shift-until-zero.ll29 ; CHECK-NEXT: [[IV_NEXT:%.*]] = add i8 [[IV]], 1
190 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
238 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
286 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
342 ; CHECK-NEXT: call void @escape_inner(i8 [[IV]], i8 [[IV]], i8 [[VAL_SHIFTED]], i1 [[LOOP_IVCHEC…
446 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 2
552 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
600 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
1047 ; IV must really be a PHI
1053 ; CHECK-NEXT: [[IV:%.*]] = add i8 0, 0
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/X86/
H A Dpr46943.ll16 ; CHECK-NEXT: [[IV:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
17 ; CHECK-NEXT: call void @use(i8 zeroext [[IV]])
18 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
46 ; CHECK-NEXT: [[IV:%.*]] = phi i8 [ 127, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
47 ; CHECK-NEXT: call void @use(i8 zeroext [[IV]])
48 ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], -1
76 ; CHECK-NEXT: [[IV:%.*]] = phi i8 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
77 ; CHECK-NEXT: call void @use(i8 zeroext [[IV]])
78 ; CHECK-NEXT: [[IV_NEXT]] = add nuw i8 [[IV]], 1
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A Dduplicate-phis.ll15 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
18 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
19 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[IV]], 1000
48 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
51 ; CHECK-NEXT: [[IV_WIDE:%.*]] = zext i32 [[IV]] to i64
53 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
54 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[IV]], 1000
88 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
93 ; CHECK-NEXT: [[IV_WIDE:%.*]] = zext i32 [[IV]] to i64
95 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DSCCPSolver.cpp470 if (IV.isOverdefined()) in pushToWorkList()
477 pushToWorkList(IV, V); in pushToWorkListMsg()
485 pushToWorkList(IV, V); in markConstant()
490 if (!IV.markOverdefined()) in markOverdefined()
498 pushToWorkList(IV, V); in markOverdefined()
570 pushToWorkList(IV, V); in mergeInValue()
752 PhiState.mergeIn(IV); in visitPHINode()
953 if (isOverdefined(IV)) in visitUnaryOperator()
974 if (IV.isOverdefined()) in visitBinaryOperator()
1308 IV, &CB, in handleCallResult()
[all …]
/llvm-project-15.0.7/llvm/test/Verifier/
H A Dget-active-lane-mask.ll5 define <4 x i32> @t1(i32 %IV, i32 %TC) {
7 ; CHECK-NEXT: %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC)
9 %res = call <4 x i32> @llvm.get.active.lane.mask.v4i32.i32(i32 %IV, i32 %TC)
15 define i32 @t2(i32 %IV, i32 %TC) {
19 %res = call i32 @llvm.get.active.lane.mask.i32.i32(i32 %IV, i32 %TC)
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/
H A Dillegal-type.ll11 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
12 ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i128, i128* [[PTR:%.*]], i64 [[IV]]
16 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
44 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
49 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
77 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
80 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
107 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
108 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
113 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IV]], [[N:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/
H A Dpeel-to-turn-invariant-accesses-dereferenceable.ll43 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
44 ; CHECK-NEXT: [[C_3:%.*]] = icmp ult i32 [[IV]], 1000
106 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
107 ; CHECK-NEXT: [[C_3:%.*]] = icmp ult i32 [[IV]], 1000
175 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
176 ; CHECK-NEXT: [[C_3:%.*]] = icmp ult i32 [[IV]], 1000
235 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
236 ; CHECK-NEXT: [[C_3:%.*]] = icmp ult i32 [[IV]], 1000
297 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
298 ; CHECK-NEXT: [[C_3:%.*]] = icmp ult i32 [[IV]], 1000
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopPredication/
H A Dwidened.ll9 ; Consider range check of type i16 and i32, while IV is of type i64
28 ; CHECK-NEXT: [[IV_TRUNC_32:%.*]] = trunc i64 [[IV]] to i32
29 ; CHECK-NEXT: [[IV_TRUNC_16:%.*]] = trunc i64 [[IV]] to i16
39 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
43 ; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], [[LOOP]] ]
76 ; Consider an IV of type long and an array access into int array.
102 ; CHECK-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV]] to i32
114 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
115 ; CHECK-NEXT: [[LATCH_CHECK:%.*]] = icmp ult i64 [[IV]], 15
164 ; CHECK-NEXT: [[IV_TRUNC_32:%.*]] = trunc i64 [[IV]] to i32
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopPredication.cpp241 const SCEVAddRecExpr *IV; member
245 : Pred(Pred), IV(IV), Limit(Limit) {} in LoopICmp()
483 auto *LatchType = LatchCheck.IV->getType(); in generateLoopLatchCheck()
496 NewLatchCheck.IV = dyn_cast<SCEVAddRecExpr>( in generateLoopLatchCheck()
498 if (!NewLatchCheck.IV) in generateLoopLatchCheck()
574 auto *Ty = RangeCheck.IV->getType(); in widenICmpRangeCheckIncrementingLoop()
623 auto *Ty = RangeCheck.IV->getType(); in widenICmpRangeCheckDecrementingLoop()
646 if (RangeCheck.IV != PostDecLatchCheckIV) { in widenICmpRangeCheckDecrementingLoop()
673 RC.IV->getStepRecurrence(*SE)->isOne() && in normalizePredicate()
705 auto *RangeCheckIV = RangeCheck->IV; in widenICmpRangeCheck()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Doverflowing-iv.ll11 ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
12 ; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], [[LEN:%.*]]
56 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
57 ; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], [[LEN:%.*]]
60 ; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[IV]], 4
102 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1
106 ; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[IV]], 4
149 ; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
153 ; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[IV]], 4
195 ; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
[all …]

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