Lines Matching refs:IV
17 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
18 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
21 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
22 ; CHECK-NEXT: store i32 [[IV]], i32* @A, align 4
51 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
56 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
57 ; CHECK-NEXT: store i32 [[IV]], i32* @A, align 4
88 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
89 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
92 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A, align 4
93 ; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[IV]], [[M:%.*]]
96 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
97 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A, align 4
134 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
135 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[UMIN]]
138 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
139 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A, align 4
171 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
172 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
175 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
176 ; CHECK-NEXT: store i32 [[IV]], i32* @A, align 4
207 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
208 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
211 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
212 ; CHECK-NEXT: store i32 [[IV]], i32* @A, align 4
241 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
242 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
245 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A, align 4
246 ; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[IV]], [[M:%.*]]
249 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A, align 4
250 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
278 ;; one IV when exit tests involve multiple IVs).
284 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
285 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
288 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
289 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A, align 4
315 ; We can remove the decrementing IV entirely
321 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
322 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
325 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
326 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A, align 4
359 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
360 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
363 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
364 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A, align 4
397 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
402 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
403 ; CHECK-NEXT: [[FX:%.*]] = udiv i32 [[IV]], 4
404 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A, align 4
435 ; known never taken (but may have an exit count outside the range of the IV)