Searched refs:ISDOpc (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 246 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
248 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
250 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
1563 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, in emitLogicalOp() argument
1587 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm); in emitLogicalOp()
1633 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg); in emitLogicalOp()
1660 unsigned Idx = ISDOpc - ISD::AND; in emitLogicalOp_ri()
1667 Opc = OpcTable[ISDOpc - ISD::AND][1]; in emitLogicalOp_ri()
1679 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) { in emitLogicalOp_ri()
1710 Opc = OpcTable[ISDOpc - ISD::AND][0]; in emitLogicalOp_rs()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 197 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
291 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, in emitLogicalOp() argument
298 switch (ISDOpc) { in emitLogicalOp()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 9034 unsigned ISDOpc = IsCallBr ? ISD::INLINEASM_BR : ISD::INLINEASM; in visitInlineAsm() local
9035 Chain = DAG.getNode(ISDOpc, getCurSDLoc(), in visitInlineAsm()
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