246   unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
248   unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
250   unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
1563 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp()  argument
1587     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);  in emitLogicalOp()
1608       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);  in emitLogicalOp()
1622         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);  in emitLogicalOp()
1633   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);  in emitLogicalOp()
1641 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_ri()  argument
1660     unsigned Idx = ISDOpc - ISD::AND;  in emitLogicalOp_ri()
1667     Opc = OpcTable[ISDOpc - ISD::AND][1];  in emitLogicalOp_ri()
1679   if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {  in emitLogicalOp_ri()
1686 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_rs()  argument
1710     Opc = OpcTable[ISDOpc - ISD::AND][0];  in emitLogicalOp_rs()
1714     Opc = OpcTable[ISDOpc - ISD::AND][1];  in emitLogicalOp_rs()