Home
last modified time | relevance | path

Searched refs:ILP (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dscheduler-backtracking.ll13 ; ILP-LABEL: test1:
14 ; ILP: # %bb.0:
15 ; ILP-NEXT: pushq %r14
16 ; ILP-NEXT: pushq %rbx
57 ; ILP-NEXT: retq
250 ; ILP-LABEL: test2:
288 ; ILP-NEXT: retq
456 ; ILP-LABEL: test3:
500 ; ILP-NEXT: retq
691 ; ILP-LABEL: test4:
[all …]
H A Dearly-ifcvt-remarks.ll46 ; CHECK-SAME: which cannot be hidden by available ILP.
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Barcelona/
H A Ddependency-breaking-sbb-1.s5 # implicit dependency on EFLAGS which limits the ILP. So, the hardware backend
H A Dpartial-reg-update-3.s4 # The ILP is limited by the false dependency on %dx. So, the mov cannot execute
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BtVer2/
H A Ddependency-breaking-sbb-1.s7 # implicit dependency on EFLAGS which limits the ILP. So, the hardware backend
H A Dpartial-reg-update-3.s6 # The ILP is limited by the false dependency on %dx. So, the mov cannot execute
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/BdVer2/
H A Ddependency-breaking-sbb-1.s7 # implicit dependency on EFLAGS which limits the ILP. So, the hardware backend
H A Dpartial-reg-update-3.s6 # The ILP is limited by the false dependency on %dx. So, the mov cannot execute
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Znver2/
H A Dpartial-reg-update-3.s4 # The ILP is limited by the false dependency on %dx. So, the mov cannot execute
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Znver1/
H A Dpartial-reg-update-3.s4 # The ILP is limited by the false dependency on %dx. So, the mov cannot execute
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-neon-v1i1-setcc.ll55 ; scalar setcc. If anything, it exposes more ILP.
H A Dbitfield-insert.ll526 ; 'and' with a 'movk', which would decrease ILP while using the same number of
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Znver3/
H A Dpartial-reg-update-3.s4 # The ILP is limited by the false dependency on %dx. So, the mov cannot execute
/llvm-project-15.0.7/llvm/docs/HistoricalNotes/
H A D2001-02-09-AdveComments.txt103 while providing easy ILP for single-threaded onces. But it is probably
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dschedule-regpressure-limit3.ll2 …mdgcn -mcpu=tonga -misched=gcn-ilp -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-ILP %s
4 …he scheduler when only one wave is requested. The result should be high register usage and max ILP.
8 ; GCN-ILP: NumVgprs: {{[0-9][0-9][0-9]$}}
10 ; FIXME: The machine scheduler is doing a poor job at maximizing ILP here.
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp2496 bool LStall = (!checkPref || left->SchedulingPref == Sched::ILP) && in BUCompareLatency()
2498 bool RStall = (!checkPref || right->SchedulingPref == Sched::ILP) && in BUCompareLatency()
2514 if (!checkPref || (left->SchedulingPref == Sched::ILP || in BUCompareLatency()
2515 right->SchedulingPref == Sched::ILP)) { in BUCompareLatency()
H A DSelectionDAGISel.cpp274 assert(TLI->getSchedulingPreference() == Sched::ILP && in createDefaultScheduler()
/llvm-project-15.0.7/llvm/docs/
H A DVectorizers.rst353 The Loop Vectorizer increases the instruction level parallelism (ILP) by
/llvm-project-15.0.7/llvm/docs/CommandGuide/
H A Dllvm-mca.rst595 vhaddps. Long data dependencies negatively impact the ILP (Instruction Level
605 which may limit the ILP. Last row, ``<total>``, shows a global average over all
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp719 SchedPreferenceInfo = Sched::ILP; in TargetLoweringBase()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h102 ILP, // Scheduling for ILP in low register pressure mode. enumerator
/llvm-project-15.0.7/clang/docs/
H A DLanguageExtensions.rst3896 improve instruction-level parallelism (ILP) using advanced hardware features,
3958 opportunities for ILP. Loops can be fully or partially unrolled. Full unrolling
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1949 return Sched::ILP; in getSchedulingPreference()
1964 return Sched::ILP; in getSchedulingPreference()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16831 return Sched::ILP; in getSchedulingPreference()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp124 setSchedulingPreference(Sched::ILP); in X86TargetLowering()
126 setSchedulingPreference(Sched::ILP); in X86TargetLowering()