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/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transfer-to-vector-load-store.mlir46 // CHECK-NEXT: %[[RES:.*]] = vector.load %[[MEM]][%[[IDX]], %[[IDX]]] : memref<8x8xf32>, vecto…
47 // CHECK-NEXT: vector.store %[[RES:.*]], %[[MEM]][%[[IDX]], %[[IDX]]] : memref<8x8xf32>, vect…
64 // CHECK-NEXT: %[[RES:.*]] = vector.load %[[MEM]][%[[IDX]], %[[IDX]]] : memref<8x8xf32>, vecto…
65 // CHECK-NEXT: vector.store %[[RES:.*]], %[[MEM]][%[[IDX]], %[[IDX]]] : memref<8x8xf32>, vecto…
143 // CHECK-NEXT: vector.transfer_write %[[RES]], %[[MEM]][%[[IDX]], %[[IDX]]] : vector<4xf32>, m…
159 // CHECK-NEXT: %[[RES:.*]] = vector.load %[[MEM]][%[[IDX]], %[[IDX]]] : memref<8x8xf32, #{{.*}…
160 // CHECK-NEXT: vector.store %[[RES]], %[[MEM]][%[[IDX]], %[[IDX]]] : memref<8x8xf32, #{{.*}}>,…
199 // CHECK-NEXT: %[[LOAD:.*]] = memref.load %[[MEM]][%[[IDX]], %[[IDX]]] : memref<8x8xf32>
216 // CHECK-NEXT: %[[LOAD:.*]] = memref.load %[[MEM]][%[[IDX]], %[[IDX]]] : memref<?x?xf32>
232 // CHECK-NEXT: %[[LOAD:.*]] = memref.load %[[MEM]][%[[IDX]], %[[IDX]]] : memref<8x8xf32>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dextract_vector_dynelt.ll5 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
7 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 2
9 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 3
25 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 1
27 ; GCN-DAG: s_cmp_lg_u32 [[IDX]], 3
43 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
45 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3
62 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
64 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3
66 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 4
[all …]
H A Dextract_vector_elt-f64.ll17 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
19 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
34 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
36 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
38 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3
H A Dextract_vector_elt-i64.ll34 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
48 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
63 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
65 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
80 ; GCN-DAG: s_cmp_eq_u32 [[IDX:s[0-9]+]], 1
82 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 2
84 ; GCN-DAG: s_cmp_eq_u32 [[IDX]], 3
H A Dinsert_vector_elt.v2i16.subtest-saddr.ll5 ; GCN: {{flat|global}}_load_dword [[IDX:v[0-9]+]]
11 ; GFX89-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, [[IDX]]
14 ; CI-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, [[IDX]]
H A Dinsert_vector_elt.v2i16.subtest-nosaddr.ll6 ; GCN: {{flat|global}}_load_dword [[IDX:v[0-9]+]]
11 ; GFX89: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, [[IDX]]
16 ; CI: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, [[IDX]]
/llvm-project-15.0.7/llvm/test/Transforms/ConstraintElimination/
H A Dtransfer-unsigned-facts-to-signed.ll12 ; CHECK-NEXT: [[T_1:%.*]] = icmp ult i8 [[IDX]], [[LEN]]
13 ; CHECK-NEXT: [[T_2:%.*]] = icmp sge i8 [[IDX]], 0
15 ; CHECK-NEXT: [[C_1:%.*]] = icmp sge i8 [[IDX]], 1
21 ; CHECK-NEXT: [[C_3:%.*]] = icmp sge i8 [[IDX]], 0
57 ; CHECK-NEXT: [[T_2:%.*]] = icmp sge i8 [[IDX]], 0
59 ; CHECK-NEXT: [[C_1:%.*]] = icmp sge i8 [[IDX]], 1
65 ; CHECK-NEXT: [[C_3:%.*]] = icmp sge i8 [[IDX]], 0
102 ; CHECK-NEXT: [[C_2:%.*]] = icmp sge i8 [[IDX]], 0
104 ; CHECK-NEXT: [[C_3:%.*]] = icmp sge i8 [[IDX]], 1
110 ; CHECK-NEXT: [[C_5:%.*]] = icmp sge i8 [[IDX]], 0
[all …]
H A Dtransfer-signed-facts-to-unsigned.ll7 ; CHECK-NEXT: [[IDX_POS:%.*]] = icmp sge i8 [[IDX:%.*]], 0
12 ; CHECK-NEXT: [[T_1:%.*]] = icmp ult i8 [[IDX]], [[LEN]]
48 ; CHECK-NEXT: [[IDX_POS:%.*]] = icmp sge i8 [[IDX]], 0
498 ; CHECK-NEXT: [[T_1:%.*]] = icmp uge i8 [[IDX]], 2
499 ; CHECK-NEXT: [[T_2:%.*]] = icmp uge i8 [[IDX]], 1
501 ; CHECK-NEXT: [[C_1:%.*]] = icmp uge i8 [[IDX]], 3
503 ; CHECK-NEXT: [[F_1:%.*]] = icmp ult i8 [[IDX]], 2
564 ; CHECK-NEXT: [[T_1:%.*]] = icmp uge i8 [[IDX]], 0
565 ; CHECK-NEXT: [[T_2:%.*]] = icmp uge i8 [[IDX]], 1
587 ; CHECK-NEXT: [[T_1:%.*]] = icmp ugt i8 [[IDX]], 2
[all …]
H A Dgeps-inbounds-precondition-ub-in-use-blocks.ll18 ; CHECK-NEXT: [[CMP_IDX:%.*]] = icmp ult i32 [[IDX:%.*]], [[N]]
19 ; CHECK-NEXT: [[IDX_EXT:%.*]] = zext i32 [[IDX]] to i64
53 ; CHECK-NEXT: [[CMP_IDX:%.*]] = icmp ult i32 [[IDX:%.*]], [[N]]
54 ; CHECK-NEXT: [[IDX_EXT:%.*]] = zext i32 [[IDX]] to i64
92 ; CHECK-NEXT: [[CMP_IDX:%.*]] = icmp ult i32 [[IDX:%.*]], [[N]]
93 ; CHECK-NEXT: [[IDX_EXT:%.*]] = zext i32 [[IDX]] to i64
135 ; CHECK-NEXT: [[CMP_IDX:%.*]] = icmp ult i32 [[IDX:%.*]], [[N]]
136 ; CHECK-NEXT: [[IDX_EXT:%.*]] = zext i32 [[IDX]] to i64
180 ; CHECK-NEXT: [[IDX_EXT:%.*]] = zext i32 [[IDX]] to i64
217 ; CHECK-NEXT: [[IDX_EXT:%.*]] = zext i32 [[IDX]] to i64
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dhip.extern.shared.array.ll27 ; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
28 ; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0xc00, [[IDX]]
54 ; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
55 ; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x4000, [[IDX]]
69 ; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
70 ; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x44, [[IDX]]
85 ; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
86 ; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x48, [[IDX]]
103 ; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
104 ; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x44, [[IDX]]
[all …]
/llvm-project-15.0.7/mlir/test/Conversion/ShapeToStandard/
H A Dshape-to-standard.mlir66 // CHECK-SAME: (%[[ARG:.*]]: tensor<2x3xf32>, %[[IDX:.*]]: index) -> index
68 // CHECK: %[[RESULT:.*]] = tensor.dim %[[ARG]], %[[IDX]] : tensor<2x3xf32>
79 // CHECK-SAME: (%[[EXTENTS:.*]]: tensor<?xindex>, %[[IDX:.*]]: index) -> index
82 // CHECK: %[[RESULT:.*]] = tensor.extract %[[EXTENTS]][%[[IDX]]] : tensor<?xindex>
382 // CHECK: %[[IDX0:.*]] = arith.subi %[[IDX]], %[[DIM_DIFF0]] : index
391 // CHECK: %[[IDX1:.*]] = arith.subi %[[IDX]], %[[DIM_DIFF1]] : index
400 // CHECK: %[[IDX2:.*]] = arith.subi %[[IDX]], %[[DIM_DIFF2]] : index
472 // CHECK: %[[IDX0:.*]] = arith.subi %[[IDX]], %[[DIM_DIFF0]] : index
481 // CHECK: %[[IDX1:.*]] = arith.subi %[[IDX]], %[[DIM_DIFF1]] : index
490 // CHECK: %[[IDX2:.*]] = arith.subi %[[IDX]], %[[DIM_DIFF2]] : index
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IRCE/
H A Drc-negative-bound.ll19 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
20 ; CHECK-NEXT: [[ABC:%.*]] = icmp slt i32 [[IDX]], -9
68 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
69 ; CHECK-NEXT: [[ABC:%.*]] = icmp slt i32 [[IDX]], -9
130 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
216 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
295 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
296 ; CHECK-NEXT: [[ABC:%.*]] = icmp ult i32 [[IDX]], -9
346 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
410 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
[all …]
H A Dranges_of_different_types.ll34 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
35 ; CHECK-NEXT: [[IDX_OFFSET:%.*]] = add i32 [[IDX]], 13
135 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
136 ; CHECK-NEXT: [[IDX_OFFSET:%.*]] = sub i32 [[IDX]], 13
253 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
254 ; CHECK-NEXT: [[IDX_OFFSET:%.*]] = add i32 [[IDX]], 13
352 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
455 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
541 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
644 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
[all …]
H A Dmultiple-access-no-preloop.ll21 ; CHECK-NEXT: [[IDX:%.*]] = phi i32 [ [[IDX_NEXT:%.*]], [[IN_BOUNDS_B:%.*]] ], [ 0, [[LOOP_PREHE…
22 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
23 ; CHECK-NEXT: [[ABC_A:%.*]] = icmp slt i32 [[IDX]], [[LEN_A]]
26 ; CHECK-NEXT: [[ADDR_A:%.*]] = getelementptr i32, i32* [[ARR_A:%.*]], i32 [[IDX]]
28 ; CHECK-NEXT: [[ABC_B:%.*]] = icmp slt i32 [[IDX]], [[LEN_B]]
31 ; CHECK-NEXT: [[ADDR_B:%.*]] = getelementptr i32, i32* [[ARR_B:%.*]], i32 [[IDX]]
H A Dconjunctive-checks.ll20 ; CHECK-NEXT: [[IDX:%.*]] = phi i32 [ [[IDX_NEXT:%.*]], [[IN_BOUNDS:%.*]] ], [ 0, [[LOOP_PREHEAD…
21 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
22 ; CHECK-NEXT: [[IDX_FOR_ABC:%.*]] = add i32 [[IDX]], 4
112 ; CHECK-NEXT: [[IDX:%.*]] = phi i32 [ [[IDX_NEXT:%.*]], [[IN_BOUNDS:%.*]] ], [ 0, [[LOOP_PREHEAD…
113 ; CHECK-NEXT: [[IDX_NEXT]] = add i32 [[IDX]], 1
114 ; CHECK-NEXT: [[ABC_A:%.*]] = icmp slt i32 [[IDX]], [[LEN_A]]
115 ; CHECK-NEXT: [[ABC_B:%.*]] = icmp slt i32 [[IDX]], [[LEN_B]]
119 ; CHECK-NEXT: [[ADDR_A:%.*]] = getelementptr i32, i32* [[ARR_A:%.*]], i32 [[IDX]]
121 ; CHECK-NEXT: [[ADDR_B:%.*]] = getelementptr i32, i32* [[ARR_B:%.*]], i32 [[IDX]]
/llvm-project-15.0.7/mlir/test/Conversion/MemRefToSPIRV/
H A Dmemref-to-spirv.mlir69 // CHECK-SAME: (%[[SRC:.+]]: memref<4xi1>, %[[IDX:.+]]: index)
89 // CHECK-SAME: %[[IDX:.+]]: index
129 // CHECK: %[[IDX:.+]] = spv.UMod %[[ZERO]], %[[FOUR2]] : i32
130 // CHECK: %[[BITS:.+]] = spv.IMul %[[IDX]], %[[EIGHT]] : i32
154 // CHECK: %[[IDX:.+]] = spv.UMod %[[ZERO]], %[[FOUR2]] : i32
155 // CHECK: %[[BITS:.+]] = spv.IMul %[[IDX]], %[[EIGHT]] : i32
218 // CHECK: %[[IDX:.+]] = spv.UMod %[[ZERO]], %[[FOUR]] : i32
245 // CHECK: %[[IDX:.+]] = spv.UMod %[[ZERO]], %[[FOUR]] : i32
329 // CHECK: %[[IDX:.+]] = spv.UMod %[[ZERO]], %[[FOUR2]] : i32
330 // CHECK: %[[BITS:.+]] = spv.IMul %[[IDX]], %[[EIGHT]] : i32
[all …]
/llvm-project-15.0.7/polly/test/ScopInfo/
H A Dgranularity_same_name.ll1 …-names=0 -polly-print-scops -disable-output < %s | FileCheck %s -match-full-lines -check-prefix=IDX
3 …-names=0 -polly-print-scops -disable-output < %s | FileCheck %s -match-full-lines -check-prefix=IDX
45 ; IDX: Statements {
46 ; IDX-NEXT: Stmt1
/llvm-project-15.0.7/llvm/test/Transforms/LoopInterchange/
H A Dpr43473-invalid-lcssa-phis-in-inner-exit.ll15 ; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds double, double* undef, i64 [[OUTER_IV]]
19 ; CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[IDX]], align 8
20 ; CHECK-NEXT: store double undef, double* [[IDX]], align 8
63 ; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds double, double* undef, i64 [[OUTER_IV]]
67 ; CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[IDX]], align 8
68 ; CHECK-NEXT: store double undef, double* [[IDX]], align 8
/llvm-project-15.0.7/llvm/test/Transforms/GVN/PRE/
H A Dload-pre-metadata-accsess-group.ll7 ; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds i32, i32* [[BB:%.*]], i64 1
10 ; CHECK-NEXT: store i32 [[TMP0]], i32* [[IDX]], align 4
23 ; CHECK-NEXT: [[DOTPRE]] = load i32, i32* [[IDX]], align 4, !llvm.access.group !0
57 ; CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds i32, i32* [[BB:%.*]], i64 1
60 ; CHECK-NEXT: store i32 [[TMP0]], i32* [[IDX]], align 4
71 ; CHECK-NEXT: [[DOTPRE1]] = load i32, i32* [[IDX]], align 4, !llvm.access.group !1
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/
H A Dload-insert-store.ll132 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 4
149 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 2
165 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 2
181 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 2
198 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 4
218 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 4
239 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[IDX:%.*]], 17
276 ; CHECK-NEXT: [[IDX_FROZEN:%.*]] = freeze i32 [[IDX:%.*]]
313 ; CHECK-NEXT: [[TMP0:%.*]] = freeze i32 [[IDX:%.*]]
379 ; CHECK-NEXT: [[IDX_FROZEN:%.*]] = freeze i32 [[IDX:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsub-gep.ll8 ; CHECK-NEXT: [[P2_IDX:%.*]] = shl nsw i64 [[IDX:%.*]], 2
21 ; CHECK-NEXT: [[P2_IDX:%.*]] = shl i64 [[IDX:%.*]], 2
34 ; CHECK-NEXT: [[P2_IDX:%.*]] = shl nsw i64 [[IDX:%.*]], 2
47 ; CHECK-NEXT: [[P2_IDX:%.*]] = shl nuw nsw i64 [[IDX:%.*]], 2
60 ; CHECK-NEXT: [[P2_IDX:%.*]] = shl i64 [[IDX:%.*]], 2
73 ; CHECK-NEXT: [[IDX_TR:%.*]] = trunc i64 [[IDX:%.*]] to i32
89 ; CHECK-NEXT: [[P2_IDX_NEG:%.*]] = mul i64 [[IDX:%.*]], -4
102 ; CHECK-NEXT: [[P2_IDX_NEG:%.*]] = mul i64 [[IDX:%.*]], -4
115 ; CHECK-NEXT: [[P2_IDX_NEG:%.*]] = mul i64 [[IDX:%.*]], -4
170 ; CHECK-NEXT: [[P2_IDX:%.*]] = shl nsw i64 [[IDX:%.*]], 3
[all …]
H A Dbitcast-vec-canon.ll77 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i32 [[IDX:%.*]]
90 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i32> undef, i32 [[X:%.*]], i567 [[IDX:%.*]]
101 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <vscale x 3 x i32> undef, i32 [[X:%.*]], i567 [[IDX:%…
118 ; CHECK-NEXT: [[I:%.*]] = insertelement <3 x i64> undef, i64 [[XB]], i32 [[IDX:%.*]]
132 ; CHECK-NEXT: [[I:%.*]] = insertelement <3 x i64> undef, i64 [[XB]], i32 [[IDX:%.*]]
145 ; CHECK-NEXT: [[I:%.*]] = insertelement <3 x i64> undef, i64 [[XB]], i32 [[IDX:%.*]]
H A Dbitcast-vec-canon-inseltpoison.ll77 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i32 [[IDX:%.*]]
90 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i32> undef, i32 [[X:%.*]], i567 [[IDX:%.*]]
101 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <vscale x 3 x i32> undef, i32 [[X:%.*]], i567 [[IDX:%…
118 ; CHECK-NEXT: [[I:%.*]] = insertelement <3 x i64> poison, i64 [[XB]], i32 [[IDX:%.*]]
132 ; CHECK-NEXT: [[I:%.*]] = insertelement <3 x i64> poison, i64 [[XB]], i32 [[IDX:%.*]]
145 ; CHECK-NEXT: [[I:%.*]] = insertelement <3 x i64> poison, i64 [[XB]], i32 [[IDX:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Dphi-of-ops-loads.ll12 ; CHECK-NEXT: [[IDX:%.*]] = phi i8 [ 0, [[BB56]] ], [ [[INC:%.*]], [[BB229]] ]
16 ; CHECK-NEXT: [[INC]] = add i8 [[IDX]], 1
48 ; CHECK-NEXT: [[IDX:%.*]] = phi i8 [ 0, [[BB56]] ], [ [[INC:%.*]], [[BB229]] ]
54 ; CHECK-NEXT: [[INC]] = add i8 [[IDX]], 1
87 ; CHECK-NEXT: [[IDX:%.*]] = phi i8 [ 0, [[BB56]] ], [ [[INC:%.*]], [[BB229]] ]
93 ; CHECK-NEXT: [[INC]] = add i8 [[IDX]], 1
/llvm-project-15.0.7/libclc/generic/lib/math/
H A Dtables.h38 #define USE_TABLE(NAME, IDX) \ argument
39 TABLE_MANGLE(NAME)(IDX)

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