Home
last modified time | relevance | path

Searched refs:ID0 (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.td22 def ID0 : Register<"ID0">;
23 def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
H A DSPIRVRegisterInfo.cpp22 SPIRVRegisterInfo::SPIRVRegisterInfo() : SPIRVGenRegisterInfo(SPIRV::ID0) {} in SPIRVRegisterInfo()
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-distribution.mlir106 // CHECK-SAME: (%[[ID0:.*]]: index, %[[ID1:.*]]: index
108 // CHECK-NEXT: %[[EXA:.*]] = vector.extract_map %{{.*}}[%[[ID0]], %[[ID1]]] : vector<64x4x32xf3…
109 // CHECK-NEXT: %[[EXB:.*]] = vector.extract_map %{{.*}}[%[[ID0]], %[[ID1]]] : vector<64x4x32xf3…
111 // CHECK-NEXT: %[[INS:.*]] = vector.insert_map %[[ADD]], %[[ADDV]][%[[ID0]], %[[ID1]]] : vector…
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dfuse-with-reshape-by-collapsing.mlir479 // CHECK: %[[ID0:.+]] = linalg.index 0
480 // CHECK-DAG: %[[T0:.+]] = arith.remui %[[ID0]], %[[C4]]
481 // CHECK-DAG: %[[T1:.+]] = arith.divui %[[ID0]], %[[C4]]
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp2048 Intrinsic::ID ID0 = Op0->getIntrinsicID(); in visitCallInst() local
2049 if (ID0 != Intrinsic::hexagon_V6_vandqrt && in visitCallInst()
2050 ID0 != Intrinsic::hexagon_V6_vandqrt_128B) in visitCallInst()