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Searched refs:Higher (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp167 Node *rotateLeft(Node *Lower, Node *Higher);
168 Node *rotateRight(Node *Lower, Node *Higher);
666 RangeTree::Node *RangeTree::rotateLeft(Node *Lower, Node *Higher) { in rotateLeft() argument
667 assert(Higher->Right == Lower); in rotateLeft()
674 Higher->Right = Lower->Left; in rotateLeft()
675 update(Higher); in rotateLeft()
676 Lower->Left = Higher; in rotateLeft()
682 assert(Higher->Left == Lower); in rotateRight()
689 Higher->Left = Lower->Right; in rotateRight()
690 update(Higher); in rotateRight()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.h71 Higher, enumerator
458 SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER); in getAddrNonPICSym64() local
461 DAG.getNode(MipsISD::Higher, DL, Ty, Higher)); in getAddrNonPICSym64()
H A DMipsSEISelDAGToDAG.cpp1244 const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue(); in trySelect() local
1249 SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32); in trySelect()
1280 if (Higher) in trySelect()
1292 (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal, in trySelect()
1309 const bool HiResNonZero = Highest || Higher; in trySelect()
H A DRelocation.txt33 MipsISD::{Highest, Higher, Hi, Lo}) depending upon relocation model,
H A DMipsRegisterInfo.td158 // Higher half of 64-bit FP registers.
H A DMipsInstrInfo.td65 def MipsHigher : SDNode<"MipsISD::Higher", SDTIntUnaryOp>;
H A DMipsISelLowering.cpp173 case MipsISD::Higher: return "MipsISD::Higher"; in getTargetNodeName()
/llvm-project-15.0.7/libc/docs/
H A Dmath.rst113 Higher Math Functions
151 Accuracy of Higher Math Functions
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dstore_stk.ll13 ;;; | | Higher address
24 ;;; | | Higher address
56 ;;; | | Higher address
H A Dload_stk.ll13 ;;; | | Higher address
24 ;;; | | Higher address
56 ;;; | | Higher address
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrControl.td60 /// EQ—Equal HI—Higher
/llvm-project-15.0.7/llvm/docs/CommandGuide/
H A Dllvm-exegesis.rst226 Higher values lead to more accurate measurements but lengthen the benchmark.
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Vector/
H A Dload_stk_ldvm.ll13 ;;; | | Higher address
24 ;;; | | Higher address
56 ;;; | | Higher address
H A Dstore_stk_stvm.ll13 ;;; | | Higher address
24 ;;; | | Higher address
56 ;;; | | Higher address
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dneon-instructions.txt199 # Vector Compare Mask Higher or Same (Unsigned Integer)
211 # Vector Compare Mask Higher (Unsigned Integer)
1565 # Scalar Compare Unsigned Higher Or Same
1584 # Scalar Compare Unsigned Higher
/llvm-project-15.0.7/mlir/docs/Dialects/
H A DVector.md169 Higher-dimensional `vector`s are ubiquitous in modern HPC hardware. One way to
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Vector/IR/
H A DVectorOps.td2341 Higher levels typically lower matrix multiplications into 'vector.contract'
2399 Higher levels typically lower matrix tranpositions into 'vector.transpose'
/llvm-project-15.0.7/llvm/docs/AMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack/
H A DAMDGPUDwarfExtensionAllowLocationDescriptionOnTheDwarfExpressionStack.md25 - [4.6 Higher Order Operations](#higher-order-operations)
908 ## 4.6 Higher Order Operations