Searched refs:Hi64 (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1274 SDValue Hi64 = in LowerCall_64() local
1279 Hi64)); in LowerCall_64()
2846 SDValue Hi64 = in LowerF128Load() local
2865 Hi64, in LowerF128Load()
2872 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1), in LowerF128Load()
2899 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, in LowerF128Store() local
2914 DAG.getStore(StNode->getChain(), dl, SDValue(Hi64, 0), in LowerF128Store()
2967 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS() local
2979 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); in LowerFNEGorFABS()
2981 Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode()); in LowerFNEGorFABS()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 1326 SDValue Hi64 = in lowerLoadF128() local
1339 SDValue(InFP128, 0), Hi64, SubRegEven); in lowerLoadF128()
1343 SDValue(Hi64.getNode(), 1)}; in lowerLoadF128()
1448 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i64, in lowerStoreF128() local
1468 DAG.getStore(StNode->getChain(), DL, SDValue(Hi64, 0), HiPtr, in lowerStoreF128()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorCombine.cpp | 1101 Value *Hi64 = Builder.CreateBitCast(Hi, Int64Ty); in vralignb() local
1104 Value *Call = Builder.CreateCall(FI, {Hi64, Lo64, Amt}); in vralignb()
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