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Searched refs:HasDisjunctSubRegs (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/test/TableGen/
H A DConcatenatedSubregs.td102 // CHECK: HasDisjunctSubRegs: 1
107 // CHECK: HasDisjunctSubRegs: 1
120 // CHECK: HasDisjunctSubRegs: 1
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.h155 bool HasDisjunctSubRegs; member
338 bool HasDisjunctSubRegs; variable
H A DCodeGenRegisters.cpp157 HasDisjunctSubRegs(false), SubRegsComplete(false), in CodeGenRegister()
273 HasDisjunctSubRegs = ExplicitSubRegs.size() > 1; in computeSubRegs()
296 HasDisjunctSubRegs |= ESR->HasDisjunctSubRegs; in computeSubRegs()
2160 RC.HasDisjunctSubRegs = false; in computeDerivedInfo()
2163 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; in computeDerivedInfo()
H A DRegisterInfoEmitter.cpp1429 << (RC.HasDisjunctSubRegs?"true":"false") in runTargetDesc()
1742 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1779 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; in debugDump()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h64 const bool HasDisjunctSubRegs; variable
H A DMachineRegisterInfo.h213 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; in shouldTrackSubRegLiveness()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp364 if (!RC.HasDisjunctSubRegs) in getLaneMaskForMO()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1368 if (RegClass->HasDisjunctSubRegs) { in canRenameUpToDef()