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Searched refs:HVC (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVectorCombine.cpp252 HexagonVectorCombine &HVC; member in __anon2c83e0c90111::AlignVectors
428 return HVC.getFullValue(HVC.getBoolTy(ElemCount)); in getMask()
430 return HVC.getFullValue(HVC.getBoolTy()); in getMask()
477 if (HVC.isZero(Mask)) in createAlignedLoad()
487 if (HVC.isZero(Mask) || HVC.isUndef(Val) || HVC.isUndef(Mask)) in createAlignedStore()
753 AlignVal = HVC.getConstInt(Diff); in realignGroup()
789 auto *True = HVC.getFullValue(HVC.getBoolTy(ScLen)); in realignGroup()
858 AccumM = HVC.insertb(Builder, AccumM, HVC.vbytes(Builder, Mask), in realignGroup()
860 AccumV = HVC.insertb(Builder, AccumV, HVC.vbytes(Builder, Pay), in realignGroup()
881 if (!HVC.isUndef(Val) && !HVC.isZero(Mask)) { in realignGroup()
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/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-virtexts.arm.txt3 # HVC (ARM)
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h684 case ARM::HVC: in isIndirectCall()
H A DARMScheduleA57.td119 "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",
H A DARMInstrInfo.td2770 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2775 // Even though HVC isn't predicable, it's encoding includes a condition field.
H A DARMInstrThumb2.td4224 // Alias for HVC without the ".w" optional width specifier
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td1245 def : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, S…
H A DAArch64SchedKryoDetails.td477 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
H A DAArch64InstrInfo.td2531 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp719 case ARM::HVC: { in checkDecodedInstruction()