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Searched refs:GeneratePressureSet (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/TableGen/
H A Dbare-minimum-psets.td27 let GeneratePressureSet = 0 in {
38 let GeneratePressureSet = 0;
H A Dempty-psets.td10 let GeneratePressureSet = 0;
H A Dinhibit-pset.td30 let GeneratePressureSet = 0;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td354 let GeneratePressureSet = 0;
362 let GeneratePressureSet = 0;
372 let GeneratePressureSet = 0;
533 let GeneratePressureSet = 0;
540 let GeneratePressureSet = 0;
585 let GeneratePressureSet = 0;
696 } // End GeneratePressureSet = 0
705 let GeneratePressureSet = 0 in {
855 } // End GeneratePressureSet = 0
857 let GeneratePressureSet = 0 in {
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/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp742 GeneratePressureSet = R->getValueAsBit("GeneratePressureSet"); in CodeGenRegisterClass()
826 GeneratePressureSet = false; in CodeGenRegisterClass()
853 GeneratePressureSet |= Super.GeneratePressureSet; in inheritProperties()
1943 if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet) in computeRegUnitSets()
2073 assert((!RegClassUnitSets[RCIdx].empty() || !RC.GeneratePressureSet) && in computeRegUnitSets()
H A DCodeGenRegisters.h344 bool GeneratePressureSet; variable
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td288 bit GeneratePressureSet = true;