| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoC.td | 811 def : CompressPat<(SUB GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
813 def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
816 def : CompressPat<(XOR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
818 def : CompressPat<(OR GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
819 (C_OR GPRC:$rs1, GPRC:$rs2)>;
821 def : CompressPat<(OR GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
823 def : CompressPat<(AND GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
826 def : CompressPat<(AND GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
834 def : CompressPat<(SUBW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
836 def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
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| H A D | RISCVRegisterInfo.td | 74 // are not part of GPRC, the most restrictive register class used by the
157 def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 724 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
790 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in prepareDynamicAlloca() local
831 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
839 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
933 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
947 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
978 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore() local
1022 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRBitSpilling() local
1140 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRBitRestore() local
1605 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in eliminateFrameIndex() local
[all …]
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| H A D | PPCRegisterInfo.td | 281 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
289 let AltOrders = [(add (sub GPRC, R2), R2),
313 def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
465 def gprc : RegisterOperand<GPRC> {
537 def spe4rc : RegisterOperand<GPRC> {
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| H A D | PPCISelLowering.cpp | 11601 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in EmitPartwordAtomicBinary() local
11607 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11608 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11611 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11612 Register Tmp3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11613 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11703 Register SReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
11710 ValueReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
12075 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in emitProbedAlloca() local
12174 MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
[all …]
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| H A D | PPCFrameLowering.cpp | 2278 const TargetRegisterClass &GPRC = PPC::GPRCRegClass; in addScavengingSpillSlot() local
2280 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
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| H A D | PPCInstrVSX.td | 2656 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>;
2658 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>;
2660 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>;
2662 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>;
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| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | asym-regclass-copy.ll | 5 ; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with
6 ; GPRC is handled correctly. When it was not, this test would assert.
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| H A D | aix-csr-alloc.ll | 10 ; AIX-32: AllocationOrder(GPRC) = [ $r3 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $r12 $r0 $r31 $r30 $r29 $…
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| /llvm-project-15.0.7/llvm/test/MC/RISCV/ |
| H A D | rv64c-invalid.s | 3 ## GPRC
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| H A D | rv32c-invalid.s | 4 ## GPRC
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | CodeGenerator.rst | 1124 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
1128 def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
1129 (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;
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