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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoA.td194 : Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
205 : Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
219 : Pat<(intrin GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
221 (AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
273 (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 2)>;
275 (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 4)>;
289 (ins GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask,
299 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
301 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;
377 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
[all …]
H A DRISCVInstrInfoZb.td819 def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>;
820 def : Pat<(or GPR:$rs1, (not GPR:$rs2)), (ORN GPR:$rs1, GPR:$rs2)>;
821 def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
958 def : Pat<(xor (and (xor GPR:$rs1, GPR:$rs3), GPR:$rs2), GPR:$rs3),
970 (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
972 (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
974 (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
976 (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
978 (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
980 (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
[all …]
H A DRISCVInstrInfo.td1127 : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
1263 def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
1267 def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
1270 def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
1271 def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
1272 def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
1273 def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
1274 def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
1275 def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
1285 def : Pat<(ineg (setge GPR:$rs1, GPR:$rs2)), (ADDI (SLT GPR:$rs1, GPR:$rs2), -1)>;
[all …]
H A DRISCVInstrInfoM.td95 def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1),
96 (assertzexti32 GPR:$rs2)), 0xffffffff),
97 (DIVU GPR:$rs1, GPR:$rs2)>;
98 def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1),
99 (assertzexti32 GPR:$rs2)), 0xffffffff),
100 (REMU GPR:$rs1, GPR:$rs2)>;
105 def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
106 (REMW GPR:$rs1, GPR:$rs2)>;
114 def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
115 (MULHU (SLLI GPR:$rs1, 32), (SLLI GPR:$rs2, 32))>;
H A DRISCVInstrInfoVVLPatterns.td492 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
498 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
679 GPR:$vl, vti.Log2SEW)>;
712 wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>;
835 wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>;
900 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
1157 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
1695 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
1701 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
1707 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
[all …]
H A DRISCVInstrInfoD.td70 def DX : ExtInfo_rr<DExt, FPR64, GPR>;
71 def DX_INX : ExtInfo_rr<ZdinxExt, FPR64INX, GPR>;
352 : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2),
353 [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;
358 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src),
359 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>;
385 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1)>;
386 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1)>;
397 def : Pat<(bitconvert (i64 GPR:$rs1)), (FMV_D_X GPR:$rs1)>;
427 def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, 0b111)>;
[all …]
H A DRISCVInstrInfoF.td115 def FX : ExtInfo_rr<FExt, FPR32, GPR>;
116 def FX_INX : ExtInfo_rr<ZfinxExt, FPR32INX, GPR>;
117 def FX_64 : ExtInfo_rr<F64Ext, FPR32, GPR>;
118 def FX_INX_64 : ExtInfo_rr<Zfinx64Ext, FPR32INX, GPR>;
153 (ins GPR:$rs1, simm12:$imm12),
421 def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>;
427 def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>;
431 def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>;
437 def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GPR:$rs)>;
581 def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td1237 def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1238 (MOVT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1242 (MOVF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1247 (MOVT32 (CMPHS32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1251 (MOVT32 (CMPHS32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
1253 (MOVF32 (CMPHS32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1257 (MOVF32 (CMPHS32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
1260 (MOVT32 (CMPLT32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1264 (MOVT32 (CMPLT32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
1266 (MOVF32 (CMPLT32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
[all …]
H A DCSKYInstrInfoF2.td93 def FLDR_S : F2_LDSTR_S<0b0, "fldr", (outs FPR32Op:$rz), (ins GPR:$rx, GPR:$ry, uimm2:$imm)>;
95 def FLDR_D : F2_LDSTR_D<0b0, "fldr", (outs FPR64Op:$rz), (ins GPR:$rx, GPR:$ry, uimm2:$imm)>;
98 def FSTR_S : F2_LDSTR_S<0b1, "fstr", (outs), (ins FPR32Op:$rz, GPR:$rx, GPR:$ry, uimm2:$imm)>;
100 def FSTR_D : F2_LDSTR_D<0b1, "fstr", (outs), (ins FPR64Op:$rz, GPR:$rx, GPR:$ry, uimm2:$imm)>;
125 (outs GPR:$vrz), (ins FPR32Op:$vrx),
129 (outs GPR:$vrz, GPR:$vry), (ins FPR64Op:$vrx),
143 (outs GPR:$vrz, GPR:$vry), (ins FPR64Op:$vrx),
144 [(set GPR:$vrz, GPR:$vry, (CSKY_BITCAST_TO_LOHI FPR64Op:$vrx))]>;
153 (outs FPR32Op:$vrz), (ins GPR:$vrx, GPR:$vry),
166 (outs FPR64Op:$vrz), (ins GPR:$vrx, GPR:$vry),
[all …]
H A DCSKYInstrFormats.td81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
200 [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
246 (ins GPR:$rz, GPR:$rx, operand:$imm12), op, []>;
463 [(set GPR:$rz, (opnode GPR:$rx, type))]>;
467 [(set GPR:$rz, (and GPR:$rx, (i32 v)))]>;
533 // Input: GPR:rx, GPR:ry
539 (ins GPR:$rx, GPR:$ry), op, [(set GPR:$rz, (opnode GPR:$rx, GPR:$ry))]> {
562 (outs GPR:$rz), (ins GPR:$rx, GPR:$ry, uimm_shift:$imm), op, []>;
565 (outs), (ins GPR:$rz, GPR:$rx, GPR:$ry, uimm_shift:$imm), op, []>;
586 (ins GPR:$rx, GPR:$ry),
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmemset-inline.ll68 ; GPR-LABEL: memset_32:
69 ; GPR: // %bb.0:
76 ; GPR-NEXT: ret
89 ; GPR: // %bb.0:
98 ; GPR-NEXT: ret
134 ; GPR-NEXT: ret
156 ; GPR-NEXT: ret
221 ; GPR-NEXT: ret
239 ; GPR-NEXT: ret
268 ; GPR-NEXT: ret
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td579 : Pat<(OpNode GPR:$rj, GPR:$rk), (Inst GPR:$rj, GPR:$rk)>;
699 def : Pat<(seteq GPR:$rj, GPR:$rk), (SLTUI (XOR GPR:$rj, GPR:$rk), 1)>;
709 def : Pat<(setne GPR:$rj, GPR:$rk), (SLTU R0, (XOR GPR:$rj, GPR:$rk))>;
718 def : Pat<(setugt GPR:$rj, GPR:$rk), (SLTU GPR:$rk, GPR:$rj)>;
719 def : Pat<(setuge GPR:$rj, GPR:$rk), (XORI (SLTU GPR:$rj, GPR:$rk), 1)>;
720 def : Pat<(setule GPR:$rj, GPR:$rk), (XORI (SLTU GPR:$rk, GPR:$rj), 1)>;
721 def : Pat<(setgt GPR:$rj, GPR:$rk), (SLT GPR:$rk, GPR:$rj)>;
722 def : Pat<(setge GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rj, GPR:$rk), 1)>;
723 def : Pat<(setle GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rk, GPR:$rj), 1)>;
727 def : Pat<(select GPR:$cond, GPR:$t, GPR:$f),
[all …]
H A DLoongArchFloat32InstrInfo.td105 def MOVGR2CF : FP_MOV<0b0000000100010100110110, "movgr2cf", CFR, GPR>;
174 def : Pat<(select GPR:$cc, FPR32:$fk, FPR32:$fj),
175 (FSEL_S FPR32:$fj, FPR32:$fk, (MOVGR2CF GPR:$cc))>;
213 // GPR -> FPR
214 def : Pat<(loongarch_movgr2fr_w_la64 GPR:$src), (MOVGR2FR_W GPR:$src)>;
215 // FPR -> GPR
219 def : Pat<(f32 (sint_to_fp GPR:$src)), (FFINT_S_W (MOVGR2FR_W GPR:$src))>;
223 // GPR -> FPR
224 def : Pat<(bitconvert (i32 GPR:$src)), (MOVGR2FR_W GPR:$src)>;
225 // FPR -> GPR
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
308 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
395 def : Pat<(LanaiSubbF GPR:$Rs1, GPR:$Rs2),
396 (SUBB_F_R GPR:$Rs1, GPR:$Rs2)>;
443 : InstRR<0b111, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI), AsmStr,
449 [(set GPR:$Rd, (shl GPR:$Rs1, GPR:$Rs2))]>;
470 def : Pat<(srl GPR:$Rs1, GPR:$Rs2),
471 (SRL_R GPR:$Rs1, (SUB_R R0, GPR:$Rs2))>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrInfo.td3902 // GPR:$dst = GPR:$a op GPR:$b
4038 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4428 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4435 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4461 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4470 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4483 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4596 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4598 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4600 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dvertex-fetch-encoding.ll6 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[G…
7 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #1 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[G…
26 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x10,0x0[[G…
27 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #3 ; encoding: [0x40,0x03,0x0[[GPR]],0x00,0x0[[G…
36 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x10,0x0[[G…
37 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x00,0x0[[G…
H A Dliterals.ll39 ; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0
40 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0
41 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0
42 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0
51 ; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0
52 ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0
53 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0
54 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dfpbr.ll3 …s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
6 ; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
21 ; GPR: not $[[GPRCC]], $[[GPRCC]]
22 ; 32-GPR: bnez $[[GPRCC]], $BB0_2
23 ; 64-GPR: bnezc $[[GPRCC]], .LBB0_2
57 ; 32-GPR: bnez $[[GPRCC]], $BB1_2
58 ; 64-GPR: bnezc $[[GPRCC]], .LBB1_2
88 ; 32-GPR: beqz $[[GPRCC]], $BB2_2
89 ; 64-GPR: beqzc $[[GPRCC]], .LBB2_2
120 ; 32-GPR: bnez $[[GPRCC]], $BB3_2
[all …]
H A Dmips64muldiv.ll4 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR
9 ; GPR - Targets with register based mul/div (i.e. MIPS32r6)
16 ; GPR: dmul $2, ${{[45]}}, ${{[45]}}
33 ; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
46 ; GPR: ddivu $2, $4, $5
56 ; GPR: ddiv $2, $4, $5
66 ; GPR: dmodu $2, $4, $5
76 ; GPR: dmod $2, $4, $5
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
268 (ins GPR:$src2, GPR:$src),
561 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
566 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
613 def : Pat<(BPFcall GPR:$dst), (JALX GPR:$dst)>;
628 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
699 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
756 [(set GPR:$dst, (OpNode ADDRri:$addr,GPR:$val))]> {
882 (ins GPR:$skb, GPR:$val),
884 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmemset-inline.ll13 ; GPR-LABEL: memset_1:
14 ; GPR: # %bb.0:
16 ; GPR-NEXT: retq
22 ; GPR-LABEL: memset_2:
23 ; GPR: # %bb.0:
28 ; GPR-NEXT: retq
34 ; GPR-LABEL: memset_4:
35 ; GPR: # %bb.0:
39 ; GPR-NEXT: retq
46 ; GPR: # %bb.0:
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_powerpc.h12 #define GPR_OFFSET(regname) (offsetof(GPR, regname))
13 #define FPR_OFFSET(regname) (sizeof(GPR) + offsetof(FPR, regname))
14 #define VMX_OFFSET(regname) (sizeof(GPR) + sizeof(FPR) + offsetof(VMX, regname))
15 #define GPR_SIZE(regname) (sizeof(((GPR *)NULL)->regname))
185 #define GPR GPR64 macro
187 #undef GPR
191 #define GPR GPR32 macro
193 #undef GPR
197 #define GPR GPR64 macro
202 (offsetof(GPR, regname) + (sizeof(((GPR *)NULL)->regname) - GPR_SIZE(reg)))
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A Ddag-isel-res-order.td12 def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
19 let OutOperandList = (outs GPR:$r1, GPR:$r0);
20 let InOperandList = (ins GPR:$t0, GPR:$t1);
H A Dpseudo-inst-expansion.td12 def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
28 let OutOperandList = (outs GPR:$rd);
33 def PSEUDO : Pseudo<(outs GPR:$rd), (ins),
34 [(set GPR:$rd, (i32 SR.Encoding))]>,
35 PseudoInstExpansion<(INSTR GPR:$rd, SR.Encoding)>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def28 // 6: GPR 32-bit value.
30 // 7: GPR 64-bit value.
32 // 8: GPR 128-bit value.
67 // 19: GPR 32-bit value.
71 // 22: GPR 64-bit value.
85 // 30: FPR 32-bit value to GPR 32-bit value.
88 // 32: FPR 64-bit value to GPR 64-bit value.
91 // 34: FPR 128-bit value to GPR 128-bit value (invalid)
100 // 40: GPR 32-bit value to FPR 32-bit value.
219 PMI_FirstGPR, // GPR
[all …]

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