Lines Matching refs:GPR
394 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
424 def top16Zero: PatLeaf<(i32 GPR:$src), [{
775 let MIOperandInfo = (ops GPR, i32imm);
786 let MIOperandInfo = (ops GPR, GPR, i32imm);
797 let MIOperandInfo = (ops GPR, i32imm);
1105 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
1126 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
1182 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
1183 // the GPR is purely vestigal at this point.
1204 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
1229 let MIOperandInfo = (ops GPR, i32imm);
1247 let MIOperandInfo = (ops GPR:$base, i32imm);
1266 let MIOperandInfo = (ops GPR:$base, i32imm);
1279 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1289 let MIOperandInfo = (ops GPR);
1299 let MIOperandInfo = (ops GPR:$addr, i32imm);
1307 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1383 let MIOperandInfo = (ops GPR:$addr, i32imm);
1394 let MIOperandInfo = (ops GPR:$addr, i32imm);
1458 let MIOperandInfo = (ops GPR, i32imm);
1469 let MIOperandInfo = (ops GPR:$base);
1529 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1531 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1542 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1544 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1557 def rsi : AsI1<opcod, (outs GPR:$Rd),
1558 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1560 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1573 def rsr : AsI1<opcod, (outs GPR:$Rd),
1574 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1576 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1602 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1604 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1615 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1629 def rsi : AsI1<opcod, (outs GPR:$Rd),
1630 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1632 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1645 def rsr : AsI1<opcod, (outs GPR:$Rd),
1646 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1648 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1672 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1674 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1677 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1679 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1683 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1684 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1686 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1690 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1691 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1693 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1704 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1706 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1709 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1710 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1712 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1713 GPR:$Rn))]>,
1716 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1717 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1719 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1720 GPR:$Rn))]>,
1733 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1735 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1747 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1749 [(opnode GPR:$Rn, GPR:$Rm)]>,
1765 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1767 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1833 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1835 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1850 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1864 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1866 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1877 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1879 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1892 def rsi : AsI1<opcod, (outs GPR:$Rd),
1893 (ins GPR:$Rn, so_reg_imm:$shift),
1895 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1934 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1936 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1947 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1960 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1962 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1975 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1977 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1999 // GPR and a constrained immediate so that we can use this to match
2001 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2003 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
2011 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
2013 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
2029 // GPR and a constrained immediate so that we can use this to match
2061 // GPR and a constrained immediate so that we can use this to match
2064 (ins GPR:$Rt, addrmode_imm12:$addr),
2066 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
2074 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
2076 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
2090 // GPR and a constrained immediate so that we can use this to match
2192 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
2194 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2366 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2368 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2372 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2374 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2376 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2378 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2380 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2382 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2384 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2386 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2388 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2390 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2393 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2394 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2396 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2397 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2400 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2401 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2412 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2428 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2431 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2465 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2466 [(brind GPR:$dst)]>,
2473 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2509 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, IIC_Br, "blx\t$func", []>,
2516 4, IIC_Br, [], (BLX GPR:$func)>,
2520 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2529 (BLX_pred GPR:$func, (ops 14, zero_reg))>,
2557 def : ARMPat<(ARMcall GPR:$func), (BLX $func)>,
2561 def : ARMPat<(ARMcall_pred GPR:$func), (BLX_pred $func)>,
2592 (ins GPR:$target, i32imm:$jt),
2594 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2607 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2609 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2628 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2655 (BX GPR:$dst)>, Sched<[WriteBr]>,
2731 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2812 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2824 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2826 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2829 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2831 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2833 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2835 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2839 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2852 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2854 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2856 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2862 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2873 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2885 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2903 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2930 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2942 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2963 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2976 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2995 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3015 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3031 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3051 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
3068 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
3092 (ins addr_offset_none:$addr, pred:$p), (outs GPR:$Rt)>;
3102 (outs GPR:$Rt)>;
3106 (outs GPR:$Rt)>;
3112 (outs GPR:$Rt)>;
3117 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
3119 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
3123 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
3141 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
3142 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
3154 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
3155 (ins GPR:$Rt, ldst_so_reg:$addr),
3167 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
3168 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3185 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
3186 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3210 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
3212 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
3214 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
3216 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
3218 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
3220 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
3222 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
3224 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
3234 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3235 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3237 [(set GPR:$Rn_wb,
3238 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3239 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3240 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3242 [(set GPR:$Rn_wb,
3243 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3244 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3245 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3247 [(set GPR:$Rn_wb,
3248 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3249 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3250 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3252 [(set GPR:$Rn_wb,
3253 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3254 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
3255 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
3257 [(set GPR:$Rn_wb,
3258 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
3263 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
3264 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
3277 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
3278 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
3282 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
3296 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
3297 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
3310 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
3311 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
3329 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
3330 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3349 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
3350 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3367 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3370 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3371 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3390 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3391 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3409 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3412 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3413 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3422 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3423 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3437 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3439 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3441 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3453 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3462 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3473 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3482 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3493 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3502 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3513 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3522 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3551 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3554 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3572 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3614 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3616 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3629 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3630 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3641 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3644 [(set GPR:$Rd, imm0_65535:$imm)]>,
3657 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>,
3662 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3668 (ins GPR:$src, imm0_65535_expr:$imm),
3672 (or (and GPR:$src, 0xffff),
3687 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3688 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3693 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3697 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3698 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3705 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3706 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3708 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3709 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3736 def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src),
3737 (SXTB16 GPR:$Src, 0)>;
3738 def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)),
3739 (SXTB16 GPR:$Src, rot_imm:$rot)>;
3742 def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS),
3743 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
3744 def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)),
3745 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>;
3761 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3762 // (UXTB16r_rot GPR:$Src, 3)>;
3763 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3764 (UXTB16 GPR:$Src, 1)>;
3765 def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src),
3766 (UXTB16 GPR:$Src, 0)>;
3767 def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)),
3768 (UXTB16 GPR:$Src, rot_imm:$rot)>;
3783 def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS),
3784 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>;
3785 def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)),
3786 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>;
3847 def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>;
3848 def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>;
3849 def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift),
3851 def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift),
3874 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3875 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3876 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3877 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3879 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3880 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3882 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3883 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3889 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3890 (SBCri GPR:$src, mod_imm_not:$imm)>;
3891 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3892 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3902 // GPR:$dst = GPR:$a op GPR:$b
3954 def : ARMV5TEPat<(saddsat GPR:$a, GPR:$b),
3955 (QADD GPR:$a, GPR:$b)>;
3956 def : ARMV5TEPat<(ssubsat GPR:$a, GPR:$b),
3957 (QSUB GPR:$a, GPR:$b)>;
4023 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4026 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
4038 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4041 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4166 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
4169 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
4181 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
4184 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
4198 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
4200 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
4211 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
4213 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
4244 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
4246 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
4256 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
4257 (BICri GPR:$src, mod_imm_not:$imm)>;
4340 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4342 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
4358 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4359 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4361 [(set GPR:$RdLo, GPR:$RdHi,
4362 (smullohi GPR:$Rn, GPR:$Rm))]>,
4366 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4367 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4369 [(set GPR:$RdLo, GPR:$RdHi,
4370 (umullohi GPR:$Rn, GPR:$Rm))]>,
4375 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4376 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4378 [(set GPR:$RdLo, GPR:$RdHi,
4379 (smullohi GPR:$Rn, GPR:$Rm))],
4380 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4384 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4385 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4387 [(set GPR:$RdLo, GPR:$RdHi,
4388 (umullohi GPR:$Rn, GPR:$Rm))],
4389 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4396 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4397 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4401 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4402 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4407 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
4408 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4425 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4426 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4428 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4432 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4433 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4435 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4444 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4446 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4452 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4454 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>,
4460 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
4461 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4463 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4467 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
4468 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4470 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4474 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
4475 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4480 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
4481 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4483 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4488 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4490 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>,
4494 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4496 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>,
4500 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4502 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>,
4506 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4508 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>,
4512 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4514 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
4518 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4520 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
4529 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4531 [(set GPRnopc:$Rd, (add GPR:$Ra,
4537 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4539 [(set GPRnopc:$Rd, (add GPR:$Ra,
4545 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4547 [(set GPRnopc:$Rd, (add GPR:$Ra,
4553 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4555 [(set GPRnopc:$Rd, (add GPR:$Ra,
4561 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4564 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4569 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4572 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4596 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4598 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4600 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4602 def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4649 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4654 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4676 def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4678 def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4680 def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4682 def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4718 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4720 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4724 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4726 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4734 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4736 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4739 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4741 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4745 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4747 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4751 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4753 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4759 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4760 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4762 (REV16 GPR:$Rn)>;
4765 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4767 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4771 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4772 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4773 (REVSH GPR:$Rm)>;
4886 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4887 (CMPri GPR:$src, mod_imm:$imm)>;
4888 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4889 (CMPrr GPR:$src, GPR:$rhs)>;
4890 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4891 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4892 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4893 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4897 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4899 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4913 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4916 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4931 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4934 GPR:$Rn, so_reg_imm:$shift)]>,
4972 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4973 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4975 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4976 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4991 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4993 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4997 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4998 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
5007 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
5008 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
5010 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
5014 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
5015 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
5017 [(set GPR:$Rd,
5018 (ARMcmov GPR:$false, so_reg_imm:$shift,
5021 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
5022 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
5024 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
5031 : ARMPseudoInst<(outs GPR:$Rd),
5032 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
5034 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
5040 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
5041 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
5043 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
5050 : ARMPseudoInst<(outs GPR:$Rd),
5051 (ins GPR:$false, i32imm:$src, cmovpred:$p),
5053 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
5058 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
5059 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
5061 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
5148 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
5153 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
5155 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
5164 (outs GPR:$newdst, GPR:$newsrc),
5165 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
5167 [(set GPR:$newdst, GPR:$newsrc,
5168 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
5226 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5228 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
5229 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5231 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
5232 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5234 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
5241 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5243 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
5244 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5246 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
5247 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
5249 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
5258 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5260 [(set GPR:$Rd, (strex_1 GPR:$Rt,
5262 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5264 [(set GPR:$Rd, (strex_2 GPR:$Rt,
5266 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5268 [(set GPR:$Rd, (strex_4 GPR:$Rt,
5271 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
5276 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5278 [(set GPR:$Rd,
5279 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
5280 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5282 [(set GPR:$Rd,
5283 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
5284 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
5286 [(set GPR:$Rd,
5287 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
5289 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
5302 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
5303 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
5304 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
5305 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
5307 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
5308 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
5309 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
5310 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
5336 …def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offs…
5337 …def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offs…
5338 …def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offs…
5609 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5611 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
5615 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5656 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5658 [(int_arm_mcr2 timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
5662 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5801 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5908 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5910 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5918 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5920 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5928 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5930 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5952 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5953 4, IIC_Br, [(brind GPR:$dst)],
5954 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5958 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst),
5960 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5970 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5971 [(set GPR:$dst, (arm_i32imm:$src))]>,
5974 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5975 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5983 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5985 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5988 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5990 [(set GPR:$dst,
5995 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5997 [(set GPR:$dst,
6002 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
6004 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
6070 (SMULBB GPR:$a, GPR:$b)>;
6071 def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)),
6072 (SMULBB GPR:$a, GPR:$b)>;
6073 def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)),
6074 (SMULBT GPR:$a, GPR:$b)>;
6075 def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b),
6076 (SMULTB GPR:$a, GPR:$b)>;
6077 def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)),
6078 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
6079 def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))),
6080 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
6081 def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))),
6082 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
6083 def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)),
6084 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
6086 def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b),
6087 (SMULBB GPR:$a, GPR:$b)>;
6088 def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b),
6089 (SMULBT GPR:$a, GPR:$b)>;
6090 def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b),
6091 (SMULTB GPR:$a, GPR:$b)>;
6092 def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b),
6093 (SMULTT GPR:$a, GPR:$b)>;
6094 def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b),
6095 (SMULWB GPR:$a, GPR:$b)>;
6096 def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b),
6097 (SMULWT GPR:$a, GPR:$b)>;
6099 def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc),
6100 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
6101 def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc),
6102 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
6103 def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc),
6104 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
6105 def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc),
6106 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>;
6107 def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc),
6108 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
6109 def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc),
6110 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>;
6113 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
6118 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
6119 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
6120 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
6121 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
6122 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
6123 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
6124 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
6127 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
6128 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
6130 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
6131 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
6132 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
6133 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
6146 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
6147 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
6148 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
6149 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
6150 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
6151 (STRH GPR:$val, addrmode3:$ptr)>;
6152 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
6153 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
6154 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
6155 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
6240 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6242 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6244 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6253 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6255 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6257 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6311 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6314 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
6317 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6320 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
6325 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6327 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6330 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6332 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6336 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6338 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6340 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6342 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6357 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6360 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6363 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6366 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6370 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
6388 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
6405 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6408 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6411 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6414 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6422 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
6424 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>;
6455 def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6456 (ins GPR:$addr, GPR:$desired, GPR:$new),
6459 def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6460 (ins GPR:$addr, GPR:$desired, GPR:$new),
6463 def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp),
6464 (ins GPR:$addr, GPR:$desired, GPR:$new),
6467 def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp),
6468 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new),