| /llvm-project-15.0.7/llvm/lib/Target/ARM/Utils/ |
| H A D | ARMBaseInfo.h | 41 GE, // Greater than or equal Greater than or equal enumerator
61 case GE: return LT; in getOppositeCondition()
62 case LT: return GE; in getOppositeCondition()
80 case ARMCC::GE: return ARMCC::LE; in getSwappedCondition()
83 case ARMCC::LE: return ARMCC::GE; in getSwappedCondition()
158 case ARMCC::GE: return "ge"; in ARMCondCodeToString()
181 .Case("ge", ARMCC::GE) in ARMCondCodeFromString()
|
| /llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/ |
| H A D | conv-trap.ll | 33 ; CHECK-NEXT: f32.ge $push[[GE:[0-9]+]]=, $0, $pop[[ZERO]]{{$}}
34 ; CHECK-NEXT: i32.and $push[[AND:[0-9]+]]=, $pop[[LT]], $pop[[GE]]{{$}}
73 ; CHECK-NEXT: f64.ge $push[[GE:[0-9]+]]=, $0, $pop[[ZERO]]{{$}}
74 ; CHECK-NEXT: i32.and $push[[AND:[0-9]+]]=, $pop[[LT]], $pop[[GE]]{{$}}
113 ; CHECK-NEXT: f32.ge $push[[GE:[0-9]+]]=, $0, $pop[[ZERO]]{{$}}
114 ; CHECK-NEXT: i32.and $push[[AND:[0-9]+]]=, $pop[[LT]], $pop[[GE]]{{$}}
153 ; CHECK-NEXT: f64.ge $push[[GE:[0-9]+]]=, $0, $pop[[ZERO]]{{$}}
154 ; CHECK-NEXT: i32.and $push[[AND:[0-9]+]]=, $pop[[LT]], $pop[[GE]]{{$}}
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTX.h | 33 GE enumerator
157 GE, enumerator
|
| /llvm-project-15.0.7/llvm/test/tools/llvm-ml/ |
| H A D | named_operators.asm | 63 t9 BYTE 5 GE 6
64 BYTE 6 GE 6
65 BYTE 7 GE 6
|
| /llvm-project-15.0.7/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | COFF_x86_64.cpp | 117 Edge GE(Kind, Offset, *GraphSymbol, Addend); in addSingleRelocation() local
120 printEdge(dbgs(), BlockToFix, GE, getCOFFX86RelocationKindName(Kind)); in addSingleRelocation()
124 BlockToFix.addEdge(std::move(GE)); in addSingleRelocation()
|
| H A D | ELF_x86_64.cpp | 243 Edge GE(Kind, Offset, *GraphSymbol, Addend); in addSingleRelocation() local
246 printEdge(dbgs(), BlockToFix, GE, x86_64::getEdgeKindName(Kind)); in addSingleRelocation()
250 BlockToFix.addEdge(std::move(GE)); in addSingleRelocation()
|
| H A D | ELF_aarch64.cpp | 324 Edge GE(Kind, Offset, *GraphSymbol, Addend); in addSingleRelocation() local
327 printEdge(dbgs(), BlockToFix, GE, aarch64::getEdgeKindName(Kind)); in addSingleRelocation()
331 BlockToFix.addEdge(std::move(GE)); in addSingleRelocation()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64GlobalISelUtils.cpp | 113 CondCode = AArch64CC::GE; in changeFCMPPredToAArch64CC()
167 CondCode2 = AArch64CC::GE; in changeVectorFCMPPredToAArch64CC()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARC/MCTargetDesc/ |
| H A D | ARCInfo.h | 35 GE = 0xa, enumerator
|
| /llvm-project-15.0.7/mlir/test/Conversion/MathToSPIRV/ |
| H A D | math-to-gl-spirv.mlir | 156 // CHECK: %[[GE:.+]] = spv.FOrdGreaterThanEqual %[[SUB]], %[[HALF]]
157 // CHECK: %[[SEL:.+]] = spv.Select %[[GE]], %[[ONE]], %[[ZERO]]
172 // CHECK: %[[GE:.+]] = spv.FOrdGreaterThanEqual %[[SUB]], %[[HALF]]
173 // CHECK: %[[SEL:.+]] = spv.Select %[[GE]], %[[ONE]], %[[ZERO]]
|
| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | mve-vcmp.s | 38 …]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
41 …]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
74 …]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
77 …]:10: {{error|note}}: condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE
126 …]]:9: {{error|note}}: condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE
173 …]:10: {{error|note}}: condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE
220 …]:10: {{error|note}}: condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE
|
| /llvm-project-15.0.7/libc/benchmarks/automemcpy/lib/ |
| H A D | ResultAnalyzer.cpp | 42 StringRef Grade::getString(const GradeEnum &GE) { in getString() argument
43 switch (GE) { in getString()
|
| /llvm-project-15.0.7/openmp/runtime/src/include/ |
| H A D | omp_lib.f90.var | 395 !DIR$ IF(__INTEL_COMPILER.GE.1400)
403 !DIR$ IF(__INTEL_COMPILER.GE.1400)
411 !DIR$ IF(__INTEL_COMPILER.GE.1400)
419 !DIR$ IF(__INTEL_COMPILER.GE.1400)
427 !DIR$ IF(__INTEL_COMPILER.GE.1400)
436 !DIR$ IF(__INTEL_COMPILER.GE.1400)
444 !DIR$ IF(__INTEL_COMPILER.GE.1400)
452 !DIR$ IF(__INTEL_COMPILER.GE.1400)
460 !DIR$ IF(__INTEL_COMPILER.GE.1400)
468 !DIR$ IF(__INTEL_COMPILER.GE.1400)
|
| H A D | omp_lib.h.var | 489 !DIR$ IF(__INTEL_COMPILER.GE.1400)
497 !DIR$ IF(__INTEL_COMPILER.GE.1400)
505 !DIR$ IF(__INTEL_COMPILER.GE.1400)
513 !DIR$ IF(__INTEL_COMPILER.GE.1400)
521 !DIR$ IF(__INTEL_COMPILER.GE.1400)
530 !DIR$ IF(__INTEL_COMPILER.GE.1400)
538 !DIR$ IF(__INTEL_COMPILER.GE.1400)
546 !DIR$ IF(__INTEL_COMPILER.GE.1400)
554 !DIR$ IF(__INTEL_COMPILER.GE.1400)
562 !DIR$ IF(__INTEL_COMPILER.GE.1400)
[all …]
|
| /llvm-project-15.0.7/flang/lib/Common/ |
| H A D | Fortran.cpp | 56 case RelationalOperator::GE: in AsFortran()
|
| H A D | Fortran-features.cpp | 56 case RelationalOperator::GE: in GetNames()
|
| /llvm-project-15.0.7/libc/benchmarks/automemcpy/include/automemcpy/ |
| H A D | ResultAnalyzer.h | 35 static StringRef getString(const GradeEnum &GE);
|
| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IntrinsicsARM.td | 96 // Writes to the GE bits.
103 // Writes to the GE bits.
106 // Writes to the GE bits.
117 // Writes to the GE bits.
137 // Writes to the GE bits.
140 // Writes to the GE bits.
151 // Writes to the GE bits.
154 // Writes to the GE bits.
157 // Writes to the GE bits.
160 // Writes to the GE bits.
[all …]
|
| /llvm-project-15.0.7/flang/include/flang/Common/ |
| H A D | Fortran.h | 41 ENUM_CLASS(RelationalOperator, LT, LE, EQ, NE, GE, GT)
|
| /llvm-project-15.0.7/flang/include/flang/Evaluate/ |
| H A D | common.h | 107 op == RelationalOperator::GE; in Satisfies()
109 return op == RelationalOperator::NE || op == RelationalOperator::GE || in Satisfies()
|
| /llvm-project-15.0.7/clang/tools/clang-fuzzer/ |
| H A D | cxx_proto.proto | 42 GE = 11; enumerator
|
| H A D | cxx_loop_proto.proto | 46 GE = 9; enumerator
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ConditionOptimizer.cpp | 232 case AArch64CC::GT: return AArch64CC::GE; in getAdjustedCmp()
233 case AArch64CC::GE: return AArch64CC::GT; in getAdjustedCmp()
|
| H A D | AArch64SchedFalkorDetails.td | 588 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT))(v2f32|v2i32p)$")>;
589 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FAC(GE|GT)(32|64)$")>;
590 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|GE|GT)(32|64|v2f32|v2i32)$")>;
591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>;
614 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f…
615 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz$")>;
669 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS|ADDP|CM(EQ|GE|HS|GT|HI))(…
670 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v1i64|v2i32|v4i16|v8i8)$")>;
671 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|LE|GE|GT|LT)(v1i64|v2i32|v4i16|v8i8)rz$")>;
735 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v16i8|v2i64|v4i32|v8i16)$")>;
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 116 case ARCCC::GE: in getOppositeBranchCondition()
123 return ARCCC::GE; in getOppositeBranchCondition()
|