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Searched refs:G8RC (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp723 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerDynamicAlloc() local
789 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in prepareDynamicAlloca() local
814 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca()
822 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in prepareDynamicAlloca()
932 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRSpilling() local
947 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
977 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRRestore() local
1021 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRBitSpilling() local
1139 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRBitRestore() local
1604 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in eliminateFrameIndex() local
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H A DPPCRegisterInfo.td297 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
302 let AltOrders = [(add (sub G8RC, X2), X2),
324 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
375 def SPILLTOVSRRC : RegisterClass<"PPC", [i64, f64], 64, (add G8RC, (sub VSFRC,
431 // Make AllocationOrder as similar as G8RC's to avoid potential spilling.
471 def g8rc : RegisterOperand<G8RC> {
H A DPPCFrameLowering.cpp2279 const TargetRegisterClass &G8RC = PPC::G8RCRegClass; in addScavengingSpillSlot() local
2280 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
H A DPPCISelLowering.cpp12074 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in emitProbedAlloca() local
12080 Register FinalStackPtr = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12081 Register FramePointer = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12082 Register ActualNegSizeReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12113 Register ScratchReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12115 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12128 Register Div = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12132 Register Mul = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12136 Register NegMod = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12174 MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
H A DPPCInstrVSX.td3319 (COPY_TO_REGCLASS (XSIEXPDP (COPY_TO_REGCLASS $A, G8RC), $B), F8RC)>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBanks.td15 def GPRRegBank : RegisterBank<"GPR", [G8RC]>;
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-csr-alloc.ll9 ; AIX-64: AllocationOrder(G8RC) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x0 $x31 $x30 $x29 $…