Searched refs:FlatScratchInitReg (Results 1 – 3 of 3) sorted by relevance
481 Register FlatScratchInitReg = Info.addFlatScratchInit(TRI); in allocateHSAUserSGPRs() local482 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); in allocateHSAUserSGPRs()483 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()598 Register FlatScratchInitReg = Info->addFlatScratchInit(*TRI); in lowerFormalArguments() local599 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); in lowerFormalArguments()600 CCInfo.AllocateReg(FlatScratchInitReg); in lowerFormalArguments()
266 Register FlatScratchInitReg = in emitEntryFunctionFlatScratchInit() local268 assert(FlatScratchInitReg); in emitEntryFunctionFlatScratchInit()271 MRI.addLiveIn(FlatScratchInitReg); in emitEntryFunctionFlatScratchInit()272 MBB.addLiveIn(FlatScratchInitReg); in emitEntryFunctionFlatScratchInit()274 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()275 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
2116 Register FlatScratchInitReg = Info.addFlatScratchInit(TRI); in allocateHSAUserSGPRs() local2117 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass); in allocateHSAUserSGPRs()2118 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()