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Searched refs:FirstReg (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp389 Register FirstReg; in CreateRegs() local
397 if (!FirstReg) FirstReg = R; in CreateRegs()
400 return FirstReg; in CreateRegs()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp494 unsigned FirstReg = 0; in ScanInstruction() local
500 if (FirstReg != 0) { in ScanInstruction()
502 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
505 FirstReg = Reg; in ScanInstruction()
509 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3365 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3382 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3531 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
4359 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4367 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
5285 unsigned SecondReg = nextReg(FirstReg); in expandLoadStoreDMacro()
5290 warnIfRegIndexIsAT(FirstReg, IDLoc); in expandLoadStoreDMacro()
5304 if (FirstReg != BaseReg || !IsLoad) { in expandLoadStoreDMacro()
5332 unsigned SecondReg = nextReg(FirstReg); in expandStoreDM1Macro()
5337 warnIfRegIndexIsAT(FirstReg, IDLoc); in expandStoreDM1Macro()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp2258 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord() argument
2317 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2319 if (FirstReg == SecondReg) in CanFormLdStDWord()
2420 Register FirstReg, SecondReg; in RescheduleOps() local
2428 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2435 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2441 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2455 .addReg(FirstReg) in RescheduleOps()
2473 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2474 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1393 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1394 Reg = FirstReg; in printVectorList()
1395 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1396 Reg = FirstReg; in printVectorList()
1397 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1398 Reg = FirstReg; in printVectorList()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1656 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
3915 unsigned FirstReg, ElementWidth; in tryParseMatrixTileList() local
3916 auto ParseRes = ParseMatrixTile(FirstReg, ElementWidth); in tryParseMatrixTileList()
3924 unsigned PrevReg = FirstReg; in tryParseMatrixTileList()
3930 SeenRegs.insert(FirstReg); in tryParseMatrixTileList()
4006 unsigned FirstReg; in tryParseVectorList() local
4017 int64_t PrevReg = FirstReg; in tryParseVectorList()
6915 unsigned FirstReg; in tryParseGPRSeqPair() local
6925 bool isXReg = XRegClass.contains(FirstReg), in tryParseGPRSeqPair()
6926 isWReg = WRegClass.contains(FirstReg); in tryParseGPRSeqPair()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4355 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4387 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
4413 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4427 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4476 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4550 unsigned FirstReg = 0; in HandleByVal() local
4566 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
4572 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) { in HandleByVal()
4573 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); in HandleByVal()
4574 ++FirstReg; in HandleByVal()
[all …]
H A DMipsISelLowering.h575 const Argument *FuncArg, unsigned FirstReg,
584 unsigned FirstReg, unsigned LastReg,
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1639 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
1645 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
1646 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
1648 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
1650 Register OldFirstReg = FirstReg; in insertSelect()
1651 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
1652 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
1657 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
H A DPPCISelLowering.cpp6780 const unsigned FirstReg = State.AllocateReg(PPC::R9); in CC_AIX() local
6782 assert(FirstReg && SecondReg && in CC_AIX()
6785 CCValAssign::getCustomReg(ValNo, ValVT, FirstReg, RegVT, LocInfo)); in CC_AIX()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp2532 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
2540 FirstReg = Count - 1; in computeCalleeSaveRegisterPairs()
2546 for (unsigned i = FirstReg; i < Count; i += RegInc) { in computeCalleeSaveRegisterPairs()
2566 bool IsFirst = i == FirstReg; in computeCalleeSaveRegisterPairs()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4773 unsigned FirstReg = Reg; in parseVectorList() local
4782 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
4936 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
4940 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); in parseVectorList()
4944 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()