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Searched refs:FirstElt (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp94 const MCRegisterCostEntry *FirstElt = in initialize() local
96 addRegisterFile(RF, ArrayRef<MCRegisterCostEntry>(FirstElt, Length)); in initialize()
/llvm-project-15.0.7/llvm/lib/IR/
H A DAsmWriter.cpp415 bool FirstElt = true; in PrintShuffleMask() local
423 if (FirstElt) in PrintShuffleMask()
424 FirstElt = false; in PrintShuffleMask()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGCall.cpp1164 llvm::Type *FirstElt = SrcSTy->getElementType(0); in EnterStructPointerForCoercedAccess() local
1171 CGF.CGM.getDataLayout().getTypeStoreSize(FirstElt); in EnterStructPointerForCoercedAccess()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp10922 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0)); in isAllConstantBuildVector() local
10923 if (!FirstElt) in isAllConstantBuildVector()
10928 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt) in isAllConstantBuildVector()
10930 ConstVal = FirstElt->getZExtValue(); in isAllConstantBuildVector()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp3573 SDValue FirstElt = in visitShuffleVector() local
3576 setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); in visitShuffleVector()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp12002 int FirstElt = Mask[FirstIndex]; in getV4X86ShuffleImm() local
12003 if (all_of(Mask, [FirstElt](int M) { return M < 0 || M == FirstElt; })) in getV4X86ShuffleImm()
12004 return (FirstElt << 6) | (FirstElt << 4) | (FirstElt << 2) | FirstElt; in getV4X86ShuffleImm()