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Searched refs:FRM (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dfrm-dependency.ll7 ; Make sure an implicit FRM dependency is added to instructions with dynamic
60 ; This uses rtz instead of dyn rounding mode so shouldn't have an FRM dependncy.
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td1163 let Uses = [FRM], mayRaiseFPException = true in {
1171 Uses = [FRM],
1185 } // Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true
1188 let Uses = [FRM], mayRaiseFPException = true in {
1196 Uses = [FRM], mayRaiseFPException = true in {
1198 } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException =…
1201 let Uses = [FRM], mayRaiseFPException = true in {
1214 Uses = [FRM], mayRaiseFPException = true in {
1222 let Uses = [FRM], mayRaiseFPException = true in {
1347 let Uses = [FRM], mayRaiseFPException = true in {
[all …]
H A DRISCVRegisterInfo.cpp108 markSuperRegs(Reserved, RISCV::FRM); in getReservedRegs()
H A DRISCVInstrInfoVPseudos.td4692 let Uses = [FRM], mayRaiseFPException = true in {
4701 let Uses = [FRM], mayRaiseFPException = true in {
4711 let Uses = [FRM], mayRaiseFPException = true in {
4720 let Uses = [FRM], mayRaiseFPException = true in {
4727 let Uses = [FRM], mayRaiseFPException = true in {
4741 let Uses = [FRM], mayRaiseFPException = true in {
4751 let Uses = [FRM], mayRaiseFPException = true in
4763 let Uses = [FRM], mayRaiseFPException = true in
4868 let Uses = [FRM], mayRaiseFPException = true in {
4881 Uses = [FRM],
H A DRISCVRegisterInfo.td592 def FRM : RISCVReg<0, "frm">;
H A DRISCVInstrInfo.td1551 def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
1552 def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
1553 def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
H A DRISCVISelLowering.cpp8525 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Src); in performFP_TO_INTCombine() local
8526 if (FRM == RISCVFPRndMode::Invalid) in performFP_TO_INTCombine()
8539 DAG.getTargetConstant(FRM, DL, XLenVT)); in performFP_TO_INTCombine()
8574 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Src); in performFP_TO_INT_SATCombine() local
8575 if (FRM == RISCVFPRndMode::Invalid) in performFP_TO_INT_SATCombine()
8593 DAG.getTargetConstant(FRM, DL, XLenVT)); in performFP_TO_INT_SATCombine()
10225 if (MI.readsRegister(RISCV::FRM)) in AdjustInstrPostInstrSelection()
10228 MachineOperand::CreateReg(RISCV::FRM, /*isDef*/ false, /*isImp*/ true)); in AdjustInstrPostInstrSelection()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp978 RISCVFPRndMode::RoundingMode FRM = in getRoundingMode() local
980 assert(FRM != RISCVFPRndMode::Invalid && "Invalid rounding mode"); in getRoundingMode()
981 return FRM; in getRoundingMode()