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Searched refs:FP_TO_UINT (Results 1 – 25 of 40) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1691 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
1692 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
1693 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
1699 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
1700 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
1701 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
1706 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
1707 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
1723 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
1845 {ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f16, 1}, in getCastInstrCost()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1781 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, in getCastInstrCost()
1782 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, in getCastInstrCost()
1916 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, in getCastInstrCost()
1917 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, in getCastInstrCost()
1918 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, in getCastInstrCost()
1919 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, in getCastInstrCost()
1920 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, in getCastInstrCost()
1921 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, in getCastInstrCost()
2029 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, in getCastInstrCost()
2030 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, in getCastInstrCost()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp705 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
738 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
740 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
742 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
744 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
746 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 }, in getCastInstrCost()
748 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 }, in getCastInstrCost()
750 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 }, in getCastInstrCost()
752 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 }, in getCastInstrCost()
754 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp176 setOperationAction(ISD::FP_TO_UINT, VT, Custom); in addTypeForNEON()
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand); in addTypeForNEON()
307 setOperationAction(ISD::FP_TO_UINT, VT, Expand); in addMVEVectorTypes()
459 setOperationAction(ISD::FP_TO_UINT, VT, Expand); in addMVEVectorTypes()
470 setOperationAction(ISD::FP_TO_UINT, MVT::v2i1, Expand); in addMVEVectorTypes()
944 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom); in ARMTargetLowering()
945 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom); in ARMTargetLowering()
1060 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in ARMTargetLowering()
1062 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom); in ARMTargetLowering()
10359 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); in LowerOperation()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davx-fp2int.ll4 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def61 DAG_INSTRUCTION(FPToUI, 1, 0, experimental_constrained_fptoui, FP_TO_UINT)
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp65 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in LoongArchTargetLowering()
89 setOperationAction(ISD::FP_TO_UINT, GRLenVT, Custom); in LoongArchTargetLowering()
136 case ISD::FP_TO_UINT: in LowerOperation()
390 case ISD::FP_TO_UINT: { in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h820 FP_TO_UINT, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp357 case ISD::FP_TO_UINT: in LegalizeOp()
551 case ISD::FP_TO_UINT: in Promote()
656 if (NewOpc == ISD::FP_TO_UINT && in PromoteFP_TO_INT()
676 if (Node->getOpcode() == ISD::FP_TO_UINT || in PromoteFP_TO_INT()
754 case ISD::FP_TO_UINT: in Expand()
H A DSelectionDAGDumper.cpp358 case ISD::FP_TO_UINT: return "fp_to_uint"; in getOperationName()
H A DLegalizeFloatTypes.cpp843 case ISD::FP_TO_UINT: Res = SoftenFloatOp_FP_TO_XINT(N); break; in SoftenFloatOperand()
1800 case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_XINT(N); break; in ExpandFloatOperand()
2113 case ISD::FP_TO_UINT: R = PromoteFloatOp_FP_TO_XINT(N, OpNo); break; in PromoteFloatOperand()
2909 case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break; in SoftPromoteHalfOperand()
H A DLegalizeIntegerTypes.cpp145 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; in PromoteIntegerResult()
666 if (N->getOpcode() == ISD::FP_TO_UINT && in PromoteIntRes_FP_TO_XINT()
667 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && in PromoteIntRes_FP_TO_XINT()
702 return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT || in PromoteIntRes_FP_TO_XINT()
2427 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; in ExpandIntegerResult()
3431 Op = DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op); in ExpandIntRes_FP_TO_UINT()
H A DLegalizeVectorTypes.cpp99 case ISD::FP_TO_UINT: in ScalarizeVectorResult()
645 case ISD::FP_TO_UINT: in ScalarizeVectorOperand()
1035 case ISD::FP_TO_UINT: in SplitVectorResult()
2739 case ISD::FP_TO_UINT: in SplitVectorOperand()
3813 case ISD::FP_TO_UINT: in WidenVectorResult()
5458 case ISD::FP_TO_UINT: in WidenVectorOperand()
H A DLegalizeDAG.cpp2622 OpToUse = IsStrict ? ISD::STRICT_FP_TO_UINT : ISD::FP_TO_UINT; in PromoteLegalFP_TO_INT()
2984 case ISD::FP_TO_UINT: in ExpandNode()
4285 case ISD::FP_TO_UINT: in ConvertNodeToLibcall()
4515 case ISD::FP_TO_UINT: in PromoteNode()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp294 case ISD::FP_TO_UINT: in getCastInstrCost()
H A DRISCVISelLowering.cpp376 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT, in RISCVTargetLowering()
519 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in RISCVTargetLowering()
573 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in RISCVTargetLowering()
789 ISD::FP_TO_UINT}, in RISCVTargetLowering()
960 setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT, in RISCVTargetLowering()
3313 case ISD::FP_TO_UINT: in LowerOperation()
3385 case ISD::FP_TO_UINT: in LowerOperation()
6844 case ISD::FP_TO_UINT: { in ReplaceNodeResults()
9043 if (Src.getOpcode() == ISD::FP_TO_UINT && in PerformDAGCombine()
9045 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), MVT::i64, in PerformDAGCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp220 setOperationAction(ISD::FP_TO_UINT, T, Expand); in initializeHVXLowering()
225 setOperationAction(ISD::FP_TO_UINT, T, Custom); in initializeHVXLowering()
293 setOperationAction(ISD::FP_TO_UINT, T, Custom); in initializeHVXLowering()
2068 assert(Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT || in LowerHvxConvertFpInt()
2072 if (Opc == ISD::FP_TO_SINT || Opc == ISD::FP_TO_UINT) { in LowerHvxConvertFpInt()
2406 case ISD::FP_TO_UINT: in LowerHvxOperation()
2472 case ISD::FP_TO_UINT: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1761 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); in HexagonTargetLowering()
1762 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); in HexagonTargetLowering()
1763 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp360 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
377 ISD::FP_TO_UINT, ISD::MUL, ISD::MULHU, in AMDGPUTargetLowering()
1172 case ISD::FP_TO_UINT: in LowerOperation()
1596 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
1747 SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2); in LowerUDIVREM64()
1748 SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc); in LowerUDIVREM64()
2565 : ISD::FP_TO_UINT, in LowerFP_TO_INT64()
2567 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP_TO_INT64()
H A DR600ISelLowering.cpp109 setOperationAction({ISD::FP_TO_UINT, ISD::FP_TO_SINT}, {MVT::i1, MVT::i64}, in R600TargetLowering()
584 case ISD::FP_TO_UINT: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp270 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); in PPCTargetLowering()
271 AddPromotedToType(ISD::FP_TO_UINT, MVT::i1, in PPCTargetLowering()
300 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom); in PPCTargetLowering()
675 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); in PPCTargetLowering()
681 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
691 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); in PPCTargetLowering()
716 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
902 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); in PPCTargetLowering()
11176 case ISD::FP_TO_UINT: in LowerOperation()
11296 case ISD::FP_TO_UINT: { in ReplaceNodeResults()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1614 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in SparcTargetLowering()
1616 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in SparcTargetLowering()
3143 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, in LowerOperation()
3489 case ISD::FP_TO_UINT: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-split-fcvt.ll231 ; FP_TO_UINT
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp209 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); // use i64 in initSPUActions()
211 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); in initSPUActions()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp221 setOperationAction(ISD::FP_TO_UINT, VT, Expand); in SystemZTargetLowering()
412 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal); in SystemZTargetLowering()
413 setOperationAction(ISD::FP_TO_UINT, MVT::v2f64, Legal); in SystemZTargetLowering()
432 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); in SystemZTargetLowering()
433 setOperationAction(ISD::FP_TO_UINT, MVT::v4f32, Legal); in SystemZTargetLowering()

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