Searched refs:FPRRC (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.h | 225 enum RISCVRegisterClass { GPRRC, FPRRC, VRRC }; enumerator
232 case RISCVRegisterClass::FPRRC: in getNumberOfRegisters()
256 return RISCVRegisterClass::FPRRC;
266 case RISCVRegisterClass::FPRRC: in getRegisterClassName()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.h | 94 GPRRC, FPRRC, VRRC, VSXRC enumerator
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| H A D | PPCTargetTransformInfo.cpp | 846 assert(ClassID == GPRRC || ClassID == FPRRC || in getNumberOfRegisters()
852 assert(ClassID == GPRRC || ClassID == FPRRC || ClassID == VRRC); in getNumberOfRegisters()
861 return ST->hasVSX() ? VSXRC : FPRRC; in getRegisterClassForType()
878 case FPRRC: return "PPC::FPRRC"; in getRegisterClassName()
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| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/ |
| H A D | reg-usage.ll | 27 ; CHECK-SCALAR-NEXT: LV(REG): RegisterClass: RISCV::FPRRC, 2 registers
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2563 const TargetRegisterClass &FPRRC = *getRegClassForTypeOnBank(DefTy, RB); in select() local
2584 return RBI.constrainGenericRegister(DefReg, FPRRC, MRI); in select()
2598 if (!RBI.constrainGenericRegister(DefReg, FPRRC, MRI)) { in select()
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