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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td23 def LTDR : UnaryRR <"ltdr", 0x22, null_frag, FP64, FP64>;
79 def TBDR : BinaryRRFe<"tbdr", 0xB351, FP64, FP64>;
90 def LCDR : UnaryRR <"lcdr", 0x23, null_frag, FP64, FP64>;
110 def HDR : UnaryRR <"hdr", 0x24, null_frag, FP64, FP64>;
114 def SQDR : UnaryRRE<"sqdr", 0xB244, null_frag, FP64, FP64>;
122 def FIDR : UnaryRRE<"fidr", 0xB37F, null_frag, FP64, FP64>;
134 def ADR : BinaryRR<"adr", 0x2A, null_frag, FP64, FP64>;
145 def AWR : BinaryRR<"awr", 0x2E, null_frag, FP64, FP64>;
154 def SDR : BinaryRR<"sdr", 0x2B, null_frag, FP64, FP64>;
164 def SWR : BinaryRR<"swr", 0x2F, null_frag, FP64, FP64>;
[all …]
H A DSystemZInstrDFP.td147 def ADTR : BinaryRRFa<"adtr", 0xB3D2, null_frag, FP64, FP64, FP64>;
151 def ADTRA : TernaryRRFa<"adtra", 0xB3D2, FP64, FP64, FP64>;
158 def SDTR : BinaryRRFa<"sdtr", 0xB3D3, null_frag, FP64, FP64, FP64>;
161 def SDTRA : TernaryRRFa<"sdtra", 0xB3D3, FP64, FP64, FP64>;
169 def MDTR : BinaryRRFa<"mdtr", 0xB3D0, null_frag, FP64, FP64, FP64>;
173 def MDTRA : TernaryRRFa<"mdtra", 0xB3D0, FP64, FP64, FP64>;
180 def DDTR : BinaryRRFa<"ddtr", 0xB3D1, null_frag, FP64, FP64, FP64>;
183 def DDTRA : TernaryRRFa<"ddtra", 0xB3D1, FP64, FP64, FP64>;
190 def QADTR : TernaryRRFb<"qadtr", 0xB3F5, FP64, FP64, FP64>;
196 def RRDTR : TernaryRRFb<"rrdtr", 0xB3F7, FP64, FP64, FP64>;
[all …]
H A DSystemZInstrFP.td46 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
106 def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>;
342 def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>;
353 def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>;
364 def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>;
382 def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>;
389 def : Pat<(any_frint FP64:$src), (FIDBR 0, FP64:$src)>;
397 def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>;
450 def SDBR : BinaryRRE<"sdbr", 0xB31B, any_fsub, FP64, FP64>;
523 def DDBR : BinaryRRE<"ddbr", 0xB31D, any_fdiv, FP64, FP64>;
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfptosi_and_fptoui.mir45 ; FP64: liveins: $f12
79 ; FP64: liveins: $f12
108 ; FP64: liveins: $f12
141 ; FP64: liveins: $f12
177 ; FP64: liveins: $d6
211 ; FP64: liveins: $d6
240 ; FP64: liveins: $d6
273 ; FP64: liveins: $d6
309 ; FP64: liveins: $f12
491 ; FP64: liveins: $d6
[all …]
H A Dsitofp_and_uitofp.mir79 ; FP64: liveins: $a0
108 ; FP64: liveins: $a0
141 ; FP64: liveins: $a0
211 ; FP64: liveins: $a0
240 ; FP64: liveins: $a0
273 ; FP64: liveins: $a0
347 ; FP64: liveins: $a0
383 ; FP64: liveins: $a0
422 ; FP64: liveins: $a0
498 ; FP64: liveins: $a0
[all …]
H A Dfloat_arithmetic_operations.mir32 ; FP64-LABEL: name: float_add
33 ; FP64: liveins: $f12, $f14
38 ; FP64: RetRA implicit $f0
62 ; FP64: liveins: $f12, $f14
67 ; FP64: RetRA implicit $f0
96 ; FP64: RetRA implicit $f0
125 ; FP64: RetRA implicit $f0
149 ; FP64: liveins: $d6, $d7
178 ; FP64: liveins: $d6, $d7
207 ; FP64: liveins: $d6, $d7
[all …]
H A Dceil_and_floor.mir30 ; FP64-LABEL: name: ceil_f32
31 ; FP64: liveins: $f12
39 ; FP64: RetRA implicit $f0
64 ; FP64-LABEL: name: ceil_f64
65 ; FP64: liveins: $d6
73 ; FP64: RetRA implicit $d0
98 ; FP64-LABEL: name: floor_f32
99 ; FP64: liveins: $f12
107 ; FP64: RetRA implicit $f0
133 ; FP64: liveins: $d6
[all …]
H A Dfcmp.mir25 ; FP64-LABEL: name: oeq_s
26 ; FP64: liveins: $f12, $f14
27 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
28 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
30 ; FP64: $v0 = COPY [[FCMP]](s32)
31 ; FP64: RetRA implicit $v0
55 ; FP64-LABEL: name: oeq_d
56 ; FP64: liveins: $d6, $d7
57 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
60 ; FP64: $v0 = COPY [[FCMP]](s32)
[all …]
H A Dfabs.mir24 ; FP64-LABEL: name: fabs_f32
25 ; FP64: liveins: $f12
26 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
27 ; FP64: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
28 ; FP64: $f0 = COPY [[FABS]](s32)
29 ; FP64: RetRA implicit $f0
50 ; FP64-LABEL: name: fabs_f64
51 ; FP64: liveins: $d6
52 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
54 ; FP64: $d0 = COPY [[FABS]](s64)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dfcmp.mir56 ; FP64-LABEL: name: false_s
57 ; FP64: liveins: $f12, $f14
59 ; FP64: $v0 = COPY [[ORi]]
60 ; FP64: RetRA implicit $v0
82 ; FP64-LABEL: name: true_s
86 ; FP64: RetRA implicit $v0
112 ; FP64-LABEL: name: uno_s
120 ; FP64: RetRA implicit $v0
148 ; FP64-LABEL: name: ord_s
184 ; FP64-LABEL: name: oeq_s
[all …]
H A Dfloat_arithmetic_operations.mir33 ; FP64-LABEL: name: float_add
34 ; FP64: liveins: $f12, $f14
39 ; FP64: RetRA implicit $f0
65 ; FP64: liveins: $f12, $f14
70 ; FP64: RetRA implicit $f0
101 ; FP64: RetRA implicit $f0
132 ; FP64: RetRA implicit $f0
158 ; FP64: liveins: $d6, $d7
189 ; FP64: liveins: $d6, $d7
220 ; FP64: liveins: $d6, $d7
[all …]
H A Dfloat_args.mir32 ; FP64: liveins: $f12, $f14
34 ; FP64: $f0 = COPY [[COPY]]
35 ; FP64: RetRA implicit $f0
57 ; FP64: liveins: $d6, $d7
59 ; FP64: $d0 = COPY [[COPY]]
60 ; FP64: RetRA implicit $d0
82 ; FP64: liveins: $a0, $a1
84 ; FP64: $f0 = COPY [[COPY]]
85 ; FP64: RetRA implicit $f0
114 ; FP64: RetRA implicit $d0
[all …]
H A Dsitofp_and_uitofp.mir27 ; FP64-LABEL: name: i32tof32
28 ; FP64: liveins: $a0
31 ; FP64: $f0 = COPY [[PseudoCVT_S_W]]
32 ; FP64: RetRA implicit $f0
55 ; FP64-LABEL: name: i32tof64
56 ; FP64: liveins: $a0
60 ; FP64: RetRA implicit $d0
88 ; FP64-LABEL: name: u32tof64
89 ; FP64: liveins: $a0
97 ; FP64: $d0 = COPY [[FSUB_D64_]]
[all …]
H A Dfloat_constants.mir24 ; FP64-LABEL: name: e_single_precision
25 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16429
26 ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572
27 ; FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
28 ; FP64: $f0 = COPY [[MTC1_]]
29 ; FP64: RetRA implicit $f0
51 ; FP64-LABEL: name: e_double_precision
52 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16389
54 ; FP64: [[LUi1:%[0-9]+]]:gpr32 = LUi 35604
57 ; FP64: $d0 = COPY [[BuildPairF64_64_]]
[all …]
H A Dfptosi_and_fptoui.mir27 ; FP64-LABEL: name: f32toi32
28 ; FP64: liveins: $f12
29 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
31 ; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
32 ; FP64: $v0 = COPY [[MFC1_]]
33 ; FP64: RetRA implicit $v0
57 ; FP64-LABEL: name: f64toi32
58 ; FP64: liveins: $d6
59 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
62 ; FP64: $v0 = COPY [[MFC1_]]
[all …]
H A Dfpext_and_fptrunc.mir26 ; FP64-LABEL: name: fpext
27 ; FP64: liveins: $f12
28 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
29 ; FP64: [[CVT_D64_S:%[0-9]+]]:fgr64 = CVT_D64_S [[COPY]]
30 ; FP64: $d0 = COPY [[CVT_D64_S]]
31 ; FP64: RetRA implicit $d0
54 ; FP64-LABEL: name: fptrunc
55 ; FP64: liveins: $d6
56 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
58 ; FP64: $f0 = COPY [[CVT_S_D64_]]
[all …]
H A Dfsqrt.mir26 ; FP64-LABEL: name: sqrt_f32
27 ; FP64: liveins: $f12
28 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
29 ; FP64: [[FSQRT_S:%[0-9]+]]:fgr32 = FSQRT_S [[COPY]]
30 ; FP64: $f0 = COPY [[FSQRT_S]]
31 ; FP64: RetRA implicit $f0
54 ; FP64-LABEL: name: sqrt_f64
55 ; FP64: liveins: $d6
56 ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
58 ; FP64: $d0 = COPY [[FSQRT_D64_]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/
H A Dfloat_args.ll16 ; FP64: bb.1.entry:
18 ; FP64-NEXT: {{ $}}
37 ; FP64: bb.1.entry:
39 ; FP64-NEXT: {{ $}}
58 ; FP64: bb.1.entry:
60 ; FP64-NEXT: {{ $}}
81 ; FP64: bb.1.entry:
83 ; FP64-NEXT: {{ $}}
110 ; FP64: bb.1.entry:
144 ; FP64: bb.1.entry:
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dsitofp_and_uitofp.ll155 ; FP64-LABEL: u32tof32:
166 ; FP64-NEXT: jr $ra
167 ; FP64-NEXT: nop
201 ; FP64-NEXT: jr $ra
202 ; FP64-NEXT: nop
224 ; FP64-LABEL: u8tof32:
236 ; FP64-NEXT: jr $ra
237 ; FP64-NEXT: nop
286 ; FP64-NEXT: nop
319 ; FP64-NEXT: nop
[all …]
H A Dfptosi_and_fptoui.ll253 ; FP64-LABEL: f64tou32:
256 ; FP64-NEXT: mfc1 $1, $f0
259 ; FP64-NEXT: mtc1 $2, $f0
271 ; FP64-NEXT: jr $ra
272 ; FP64-NEXT: nop
301 ; FP64-LABEL: f64tou16:
320 ; FP64-NEXT: jr $ra
321 ; FP64-NEXT: nop
350 ; FP64-LABEL: f64tou8:
369 ; FP64-NEXT: jr $ra
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfloat_arithmetic_operations.mir33 ; FP64-LABEL: name: float_add
34 ; FP64: liveins: $f12, $f14
39 ; FP64: RetRA implicit $f0
64 ; FP64: liveins: $f12, $f14
69 ; FP64: RetRA implicit $f0
99 ; FP64: RetRA implicit $f0
129 ; FP64: RetRA implicit $f0
154 ; FP64: liveins: $d6, $d7
184 ; FP64: liveins: $d6, $d7
214 ; FP64: liveins: $d6, $d7
[all …]
H A Dfloat_args.mir32 ; FP64: liveins: $f12, $f14
35 ; FP64: RetRA implicit $f0
56 ; FP64: liveins: $d6, $d7
59 ; FP64: RetRA implicit $d0
80 ; FP64: liveins: $a0, $a1
83 ; FP64: RetRA implicit $f0
111 ; FP64: RetRA implicit $d0
151 ; FP64: RetRA implicit $f0
186 ; FP64: liveins: $d6, $d7
196 ; FP64: RetRA implicit $d0
[all …]
H A Dsitofp_and_uitofp.mir26 ; FP64-LABEL: name: i32tof32
27 ; FP64: liveins: $a0
30 ; FP64: $f0 = COPY [[SITOFP]](s32)
31 ; FP64: RetRA implicit $f0
53 ; FP64-LABEL: name: i32tof64
54 ; FP64: liveins: $a0
58 ; FP64: RetRA implicit $d0
83 ; FP64-LABEL: name: u32tof64
84 ; FP64: liveins: $a0
90 ; FP64: $d0 = COPY [[FSUB]](s64)
[all …]
H A Dfcmp.mir27 ; FP64-LABEL: name: oeq_s
28 ; FP64: liveins: $f12, $f14
29 ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
30 ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
33 ; FP64: $v0 = COPY [[COPY2]](s32)
34 ; FP64: RetRA implicit $v0
60 ; FP64-LABEL: name: oeq_d
61 ; FP64: liveins: $d6, $d7
62 ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
66 ; FP64: $v0 = COPY [[COPY2]](s32)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A D2013-11-18-fp64-const0.ll36 ; CHECK-FP64: # %bb.0: # %BB
39 ; CHECK-FP64-NEXT: mtc1 $zero, $f1
40 ; CHECK-FP64-NEXT: mthc1 $zero, $f1
41 ; CHECK-FP64-NEXT: $BB0_1: # %CF88
43 ; CHECK-FP64-NEXT: c.ueq.d $f12, $f0
49 ; CHECK-FP64-NEXT: and $1, $2, $1
50 ; CHECK-FP64-NEXT: bnez $1, $BB0_1
51 ; CHECK-FP64-NEXT: nop
52 ; CHECK-FP64-NEXT: # %bb.2: # %CF85
53 ; CHECK-FP64-NEXT: jr $ra
[all …]

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