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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfptosi_and_fptoui.mir33 ; FP32: liveins: $f12
73 ; FP32: liveins: $f12
99 ; FP32: liveins: $f12
132 ; FP32: liveins: $f12
165 ; FP32: liveins: $d6
205 ; FP32: liveins: $d6
231 ; FP32: liveins: $d6
264 ; FP32: liveins: $d6
297 ; FP32: liveins: $f12
479 ; FP32: liveins: $d6
[all …]
H A Dsitofp_and_uitofp.mir33 ; FP32: liveins: $a0, $a1
73 ; FP32: liveins: $a0
99 ; FP32: liveins: $a0
132 ; FP32: liveins: $a0
205 ; FP32: liveins: $a0
231 ; FP32: liveins: $a0
264 ; FP32: liveins: $a0
337 ; FP32: liveins: $a0
371 ; FP32: liveins: $a0
410 ; FP32: liveins: $a0
[all …]
H A Dfloat_arithmetic_operations.mir25 ; FP32-LABEL: name: float_add
26 ; FP32: liveins: $f12, $f14
31 ; FP32: RetRA implicit $f0
55 ; FP32: liveins: $f12, $f14
60 ; FP32: RetRA implicit $f0
89 ; FP32: RetRA implicit $f0
118 ; FP32: RetRA implicit $f0
142 ; FP32: liveins: $d6, $d7
171 ; FP32: liveins: $d6, $d7
200 ; FP32: liveins: $d6, $d7
[all …]
H A Dceil_and_floor.mir20 ; FP32-LABEL: name: ceil_f32
21 ; FP32: liveins: $f12
29 ; FP32: RetRA implicit $f0
54 ; FP32-LABEL: name: ceil_f64
55 ; FP32: liveins: $d6
63 ; FP32: RetRA implicit $d0
88 ; FP32-LABEL: name: floor_f32
89 ; FP32: liveins: $f12
97 ; FP32: RetRA implicit $f0
123 ; FP32: liveins: $d6
[all …]
H A Dfcmp.mir18 ; FP32-LABEL: name: oeq_s
19 ; FP32: liveins: $f12, $f14
20 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
21 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
23 ; FP32: $v0 = COPY [[FCMP]](s32)
24 ; FP32: RetRA implicit $v0
48 ; FP32-LABEL: name: oeq_d
49 ; FP32: liveins: $d6, $d7
50 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
53 ; FP32: $v0 = COPY [[FCMP]](s32)
[all …]
H A Dfabs.mir18 ; FP32-LABEL: name: fabs_f32
19 ; FP32: liveins: $f12
20 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
21 ; FP32: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
22 ; FP32: $f0 = COPY [[FABS]](s32)
23 ; FP32: RetRA implicit $f0
44 ; FP32-LABEL: name: fabs_f64
45 ; FP32: liveins: $d6
46 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
48 ; FP32: $d0 = COPY [[FABS]](s64)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dfcmp.mir51 ; FP32-LABEL: name: false_s
52 ; FP32: liveins: $f12, $f14
54 ; FP32: $v0 = COPY [[ORi]]
55 ; FP32: RetRA implicit $v0
77 ; FP32-LABEL: name: true_s
81 ; FP32: RetRA implicit $v0
103 ; FP32-LABEL: name: uno_s
111 ; FP32: RetRA implicit $v0
139 ; FP32-LABEL: name: ord_s
175 ; FP32-LABEL: name: oeq_s
[all …]
H A Dfloat_arithmetic_operations.mir26 ; FP32-LABEL: name: float_add
27 ; FP32: liveins: $f12, $f14
32 ; FP32: RetRA implicit $f0
58 ; FP32: liveins: $f12, $f14
63 ; FP32: RetRA implicit $f0
94 ; FP32: RetRA implicit $f0
125 ; FP32: RetRA implicit $f0
151 ; FP32: liveins: $d6, $d7
182 ; FP32: liveins: $d6, $d7
213 ; FP32: liveins: $d6, $d7
[all …]
H A Dfloat_args.mir27 ; FP32: liveins: $f12, $f14
29 ; FP32: $f0 = COPY [[COPY]]
30 ; FP32: RetRA implicit $f0
52 ; FP32: liveins: $d6, $d7
54 ; FP32: $d0 = COPY [[COPY]]
55 ; FP32: RetRA implicit $d0
77 ; FP32: liveins: $a0, $a1
79 ; FP32: $f0 = COPY [[COPY]]
80 ; FP32: RetRA implicit $f0
107 ; FP32: RetRA implicit $d0
[all …]
H A Dsitofp_and_uitofp.mir21 ; FP32-LABEL: name: i32tof32
22 ; FP32: liveins: $a0
25 ; FP32: $f0 = COPY [[PseudoCVT_S_W]]
26 ; FP32: RetRA implicit $f0
49 ; FP32-LABEL: name: i32tof64
50 ; FP32: liveins: $a0
54 ; FP32: RetRA implicit $d0
77 ; FP32-LABEL: name: u32tof64
78 ; FP32: liveins: $a0
86 ; FP32: $d0 = COPY [[FSUB_D32_]]
[all …]
H A Dfloat_constants.mir18 ; FP32-LABEL: name: e_single_precision
19 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16429
20 ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572
21 ; FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
22 ; FP32: $f0 = COPY [[MTC1_]]
23 ; FP32: RetRA implicit $f0
43 ; FP32-LABEL: name: e_double_precision
44 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16389
46 ; FP32: [[LUi1:%[0-9]+]]:gpr32 = LUi 35604
49 ; FP32: $d0 = COPY [[BuildPairF64_]]
[all …]
H A Dfptosi_and_fptoui.mir20 ; FP32-LABEL: name: f32toi32
21 ; FP32: liveins: $f12
22 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
24 ; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
25 ; FP32: $v0 = COPY [[MFC1_]]
26 ; FP32: RetRA implicit $v0
50 ; FP32-LABEL: name: f64toi32
51 ; FP32: liveins: $d6
52 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
55 ; FP32: $v0 = COPY [[MFC1_]]
[all …]
H A Dfpext_and_fptrunc.mir20 ; FP32-LABEL: name: fpext
21 ; FP32: liveins: $f12
22 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
23 ; FP32: [[CVT_D32_S:%[0-9]+]]:afgr64 = CVT_D32_S [[COPY]]
24 ; FP32: $d0 = COPY [[CVT_D32_S]]
25 ; FP32: RetRA implicit $d0
48 ; FP32-LABEL: name: fptrunc
49 ; FP32: liveins: $d6
50 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
52 ; FP32: $f0 = COPY [[CVT_S_D32_]]
[all …]
H A Dfsqrt.mir20 ; FP32-LABEL: name: sqrt_f32
21 ; FP32: liveins: $f12
22 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
23 ; FP32: [[FSQRT_S:%[0-9]+]]:fgr32 = FSQRT_S [[COPY]]
24 ; FP32: $f0 = COPY [[FSQRT_S]]
25 ; FP32: RetRA implicit $f0
48 ; FP32-LABEL: name: sqrt_f64
49 ; FP32: liveins: $d6
50 ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
52 ; FP32: $d0 = COPY [[FSQRT_D32_]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/
H A Dfloat_args.ll8 ; FP32: bb.1.entry:
10 ; FP32-NEXT: {{ $}}
29 ; FP32: bb.1.entry:
31 ; FP32-NEXT: {{ $}}
50 ; FP32: bb.1.entry:
52 ; FP32-NEXT: {{ $}}
71 ; FP32: bb.1.entry:
73 ; FP32-NEXT: {{ $}}
96 ; FP32: bb.1.entry:
98 ; FP32-NEXT: {{ $}}
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dsitofp_and_uitofp.ll141 ; FP32-LABEL: u32tof32:
152 ; FP32-NEXT: jr $ra
153 ; FP32-NEXT: nop
186 ; FP32-NEXT: jr $ra
187 ; FP32-NEXT: nop
209 ; FP32-LABEL: u8tof32:
221 ; FP32-NEXT: jr $ra
222 ; FP32-NEXT: nop
273 ; FP32-NEXT: nop
305 ; FP32-NEXT: nop
[all …]
H A Dfptosi_and_fptoui.ll232 ; FP32-LABEL: f64tou32:
235 ; FP32-NEXT: mfc1 $1, $f0
238 ; FP32-NEXT: mtc1 $2, $f0
250 ; FP32-NEXT: jr $ra
251 ; FP32-NEXT: nop
279 ; FP32-LABEL: f64tou16:
298 ; FP32-NEXT: jr $ra
299 ; FP32-NEXT: nop
328 ; FP32-LABEL: f64tou8:
347 ; FP32-NEXT: jr $ra
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfloat_arithmetic_operations.mir26 ; FP32-LABEL: name: float_add
27 ; FP32: liveins: $f12, $f14
32 ; FP32: RetRA implicit $f0
57 ; FP32: liveins: $f12, $f14
62 ; FP32: RetRA implicit $f0
92 ; FP32: RetRA implicit $f0
122 ; FP32: RetRA implicit $f0
147 ; FP32: liveins: $d6, $d7
177 ; FP32: liveins: $d6, $d7
207 ; FP32: liveins: $d6, $d7
[all …]
H A Dfloat_args.mir27 ; FP32: liveins: $f12, $f14
30 ; FP32: RetRA implicit $f0
51 ; FP32: liveins: $d6, $d7
54 ; FP32: RetRA implicit $d0
75 ; FP32: liveins: $a0, $a1
78 ; FP32: RetRA implicit $f0
104 ; FP32: RetRA implicit $d0
139 ; FP32: RetRA implicit $f0
174 ; FP32: liveins: $d6, $d7
184 ; FP32: RetRA implicit $d0
[all …]
H A Dsitofp_and_uitofp.mir20 ; FP32-LABEL: name: i32tof32
21 ; FP32: liveins: $a0
24 ; FP32: $f0 = COPY [[SITOFP]](s32)
25 ; FP32: RetRA implicit $f0
47 ; FP32-LABEL: name: i32tof64
48 ; FP32: liveins: $a0
52 ; FP32: RetRA implicit $d0
74 ; FP32-LABEL: name: u32tof64
75 ; FP32: liveins: $a0
81 ; FP32: $d0 = COPY [[FSUB]](s64)
[all …]
H A Dfcmp.mir19 ; FP32-LABEL: name: oeq_s
20 ; FP32: liveins: $f12, $f14
21 ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
22 ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
25 ; FP32: $v0 = COPY [[COPY2]](s32)
26 ; FP32: RetRA implicit $v0
52 ; FP32-LABEL: name: oeq_d
53 ; FP32: liveins: $d6, $d7
54 ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
58 ; FP32: $v0 = COPY [[COPY2]](s32)
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td22 def LTER : UnaryRR <"lter", 0x32, null_frag, FP32, FP32>;
89 def LCER : UnaryRR <"lcer", 0x33, null_frag, FP32, FP32>;
96 def LPER : UnaryRR <"lper", 0x30, null_frag, FP32, FP32>;
109 def HER : UnaryRR <"her", 0x34, null_frag, FP32, FP32>;
113 def SQER : UnaryRRE<"sqer", 0xB245, null_frag, FP32, FP32>;
121 def FIER : UnaryRRE<"fier", 0xB377, null_frag, FP32, FP32>;
133 def AER : BinaryRR<"aer", 0x3A, null_frag, FP32, FP32>;
144 def AUR : BinaryRR<"aur", 0x3E, null_frag, FP32, FP32>;
153 def SER : BinaryRR<"ser", 0x3B, null_frag, FP32, FP32>;
163 def SUR : BinaryRR<"sur", 0x3F, null_frag, FP32, FP32>;
[all …]
H A DSystemZInstrFP.td45 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
51 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
91 def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>;
344 def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>;
355 def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>;
381 def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>;
388 def : Pat<(any_frint FP32:$src), (FIEBR 0, FP32:$src)>;
396 def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>;
449 def SEBR : BinaryRRE<"sebr", 0xB30B, any_fsub, FP32, FP32>;
522 def DEBR : BinaryRRE<"debr", 0xB30D, any_fdiv, FP32, FP32>;
[all …]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmve-fp-registers.s45 # FP32: vldmia r0, {d0} @ encoding: [0x90,0xec,0x02,0x0b]
49 # FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0b]
53 # FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0b]
57 # FP32: vstmia r0, {d0} @ encoding: [0x80,0xec,0x02,0x0b]
61 # FP32: vpush {{.*}} @ encoding: [0x2d,0xed,0x20,0x0b]
65 # FP32: vpush {{.*}} @ encoding: [0x2d,0xed,0x20,0x0b]
69 # FP32: vldmia r0, {s0} @ encoding: [0x90,0xec,0x01,0x0a]
73 # FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0a]
77 # FP32: vpop {{.*}} @ encoding: [0xbd,0xec,0x20,0x0a]
81 # FP32: vstmia r0, {s0} @ encoding: [0x80,0xec,0x01,0x0a]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A D2013-11-18-fp64-const0.ll15 ; CHECK-FP32: # %bb.0: # %BB
18 ; CHECK-FP32-NEXT: mtc1 $zero, $f2
19 ; CHECK-FP32-NEXT: mtc1 $zero, $f3
20 ; CHECK-FP32-NEXT: $BB0_1: # %CF88
22 ; CHECK-FP32-NEXT: c.ueq.d $f12, $f0
28 ; CHECK-FP32-NEXT: and $1, $2, $1
29 ; CHECK-FP32-NEXT: bnez $1, $BB0_1
30 ; CHECK-FP32-NEXT: nop
31 ; CHECK-FP32-NEXT: # %bb.2: # %CF85
32 ; CHECK-FP32-NEXT: jr $ra
[all …]

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