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Searched refs:FMSTAT (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/GlobalISel/
H A Darm-instruction-select-cmp.mir426 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
457 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
488 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
519 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
550 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
581 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
612 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
643 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
674 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
705 ; CHECK: FMSTAT 14 /* CC::al */, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfp16-litpool2-arm.mir94 FMSTAT 14, $noreg, implicit-def $cpsr, implicit killed $fpscr_nzcv
H A Dfp16-litpool3-arm.mir100 FMSTAT 14, $noreg, implicit-def $cpsr, implicit killed $fpscr_nzcv
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM4.td132 def : M4UnitL1I<(instregex "VMRS", "VMSR", "FMSTAT")>;
H A DARMISelLowering.h94 FMSTAT, // ARM fmstat instruction. enumerator
H A DARMScheduleM7.td437 def : InstRW<[M7VMRS], (instregex "FMSTAT")>;
H A DThumb2SizeReduction.cpp265 case ARM::FMSTAT: in isHighLatencyCPSR()
H A DARMInstructionSelector.cpp1055 CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT, in select()
H A DARMInstrVFP.td21 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
2473 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2722 def : InstAlias<"fmstat${p}", (FMSTAT pred:$p), 0>, Requires<[HasFPRegs]>;
H A DARMScheduleSwift.td671 def : InstRW<[SwiftWriteP0TwoCycle], (instregex "FMSTAT")>;
H A DARMScheduleA57.td125 def : InstRW<[WriteNoop], (instregex "VMRS", "VMSR", "FMSTAT")>;
H A DARMFastISel.cpp1452 TII.get(ARM::FMSTAT))); in ARMEmitCmp()
H A DARMBaseInstrInfo.cpp4397 if (DefMI.getOpcode() == ARM::FMSTAT) { in getOperandLatencyImpl()
H A DARMISelLowering.cpp1694 MAKE_CASE(ARMISD::FMSTAT) in getTargetNodeName()
4840 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); in getVFPCmp()
4852 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation"); in duplicateCmp()
4861 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); in duplicateCmp()
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp6252 if (Inst.getOpcode() != ARM::FMSTAT) { in DecodeForVMRSandVMSR()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp10794 case ARM::FMSTAT: in checkTargetMatchPredicate()