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Searched refs:FLD (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dmake-compressible.mir578 ; RV32-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
579 ; RV32-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
586 ; RV64-NEXT: renamable $f10_d = FLD $x10, 0 :: (load (s64) from %ir.g)
587 ; RV64-NEXT: renamable $f11_d = FLD $x10, 8 :: (load (s64) from %ir.arrayidx1)
590 renamable $f10_d = FLD renamable $x16, 0 :: (load (s64) from %ir.g)
591 renamable $f11_d = FLD renamable $x16, 8 :: (load (s64) from %ir.arrayidx1)
774 ; RV32-NEXT: renamable $f10_d = FLD $x11, 32 :: (load (s64) from %ir.arrayidx)
786 renamable $f10_d = FLD renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
787 renamable $f11_d = FLD renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
980 renamable $f10_d = FLD killed renamable $x16, 0 :: (load (s64) from %ir.g)
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMakeCompressible.cpp111 case RISCV::FLD: in log2LdstWidth()
151 Opcode == RISCV::LD || Opcode == RISCV::FLD; in isCompressibleLoad()
H A DRISCVInstrInfoD.td96 def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>;
206 def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
341 defm : LdPat<load, FLD, f64>;
H A DRISCVMergeBaseOffset.cpp338 case RISCV::FLD: in detectAndFoldOffset()
H A DRISCVInstrInfoC.td742 def : CompressPat<(FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
859 def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
H A DRISCVInstrInfo.cpp83 case RISCV::FLD: in isLoadFromStackSlot()
574 Opcode = RISCV::FLD; in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td251 defm FLD : FT_XYAI_LD<0b0010000, "fld">;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h836 FLD, enumerator
H A DX86InstrFPStack.td29 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
H A DX86SchedHaswell.td772 // FLD.
H A DX86ISelDAGToDAG.cpp1395 X86ISD::FLD, dl, VTs, Ops, MemVT, MPI, in PreprocessISelDAG()
H A DX86ISelLowering.cpp21770 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, TheVT, MMO); in FP_TO_INTHelper()
22718 Src = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, SrcVT, MPI, in LRINT_LLRINTHelper()
33455 NODE_NAME_CASE(FLD) in getTargetNodeName()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp2707 emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()