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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-fadd.mir19 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
20 ; SI-NEXT: $vgpr0 = COPY [[FADD]](s32)
26 ; VI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
27 ; VI-NEXT: $vgpr0 = COPY [[FADD]](s32)
34 ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
53 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
60 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
67 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
136 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[UV2]]
147 ; VI-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV]], [[UV2]]
[all …]
H A Dlegalize-fmad.s64.mir25 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[COPY2]]
26 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
55 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[UV4]]
58 … ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
85 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[COPY2]]
86 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
115 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[UV4]]
118 … ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FADD]](s64), [[FADD1]](s64)
H A Dlegalize-fmad.s32.mir51 ; GFX103-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
52 ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](s32)
103 ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](s32)
361 ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](s32)
370 ; GFX7-NEXT: $vgpr0 = COPY [[FADD]](s32)
379 ; GFX101-NEXT: $vgpr0 = COPY [[FADD]](s32)
388 ; GFX103-NEXT: $vgpr0 = COPY [[FADD]](s32)
415 ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](s32)
424 ; GFX7-NEXT: $vgpr0 = COPY [[FADD]](s32)
433 ; GFX101-NEXT: $vgpr0 = COPY [[FADD]](s32)
[all …]
H A Dregbankselect-fadd.mir19 ; CHECK-NEXT: [[FADD:%[0-9]+]]:vgpr(s32) = G_FADD [[COPY2]], [[COPY3]]
38 ; CHECK-NEXT: [[FADD:%[0-9]+]]:vgpr(s32) = G_FADD [[COPY2]], [[COPY1]]
57 ; CHECK-NEXT: [[FADD:%[0-9]+]]:vgpr(s32) = G_FADD [[COPY]], [[COPY2]]
75 ; CHECK-NEXT: [[FADD:%[0-9]+]]:vgpr(s32) = G_FADD [[COPY]], [[COPY1]]
H A Dcombine-fma-add-mul-post-legalize.mir25 ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
44 ; GFX9-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
63 ; GFX10-NEXT: $vgpr0 = COPY [[FADD]](s32)
82 ; GFX10-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
116 ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
135 ; GFX9-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
154 ; GFX10-NEXT: $vgpr0 = COPY [[FADD]](s32)
211 ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
261 ; GFX10-NEXT: $vgpr0 = COPY [[FADD]](s32)
330 ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
[all …]
H A Dlegalize-intrinsic-round.mir30 ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](s32)
47 ; GFX8-NEXT: $vgpr0 = COPY [[FADD]](s32)
64 ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
92 ; GFX6-NEXT: $vgpr0 = COPY [[FADD]](s32)
109 ; GFX8-NEXT: $vgpr0 = COPY [[FADD]](s32)
126 ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
164 ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
182 ; GFX8-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
200 ; GFX9-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
341 ; GFX6-NEXT: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[FADD]]
[all …]
H A Dlegalize-fsub.mir52 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
53 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
60 ; VI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
61 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
69 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
89 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
97 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
105 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FADD]](s64)
314 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
403 ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD]](s16)
[all …]
H A Dlegalize-fmad.s16.mir33 ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT2]], [[FPEXT3]]
34 ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
59 ; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[FMUL]], [[TRUNC2]]
60 ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
110 ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FADD]](s32)
175 ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
424 ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
592 ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD]](s16)
707 ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD]](s16)
878 ; GFX7-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FADD]](s16)
[all …]
H A Dcombine-fma-add-mul-pre-legalize.mir25 ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
44 ; GFX9-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
63 ; GFX10-NEXT: $vgpr0 = COPY [[FADD]](s32)
82 ; GFX10-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
116 ; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
135 ; GFX9-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
154 ; GFX10-NEXT: $vgpr0 = COPY [[FADD]](s32)
173 ; GFX10-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
210 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
264 ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dpostlegalizercombiner-extractvec-faddp.mir21 ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[EVEC]], [[EVEC1]]
22 ; CHECK: $d0 = COPY [[FADD]](s64)
52 ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[EVEC]], [[EVEC1]]
53 ; CHECK: $d0 = COPY [[FADD]](s64)
83 ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[EVEC]], [[EVEC1]]
84 ; CHECK: $s0 = COPY [[FADD]](s32)
114 ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[EVEC]], [[EVEC1]]
115 ; CHECK: $s0 = COPY [[FADD]](s32)
144 ; CHECK: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[SHUF]], [[COPY]]
145 ; CHECK: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[FADD]](<2 x s64>), [[C]](s64)
[all …]
H A Darm64-irtranslator-fmuladd.ll24 ; FPOFF: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
25 ; FPOFF: $s0 = COPY [[FADD]](s32)
H A Dlegalize-reduce-fadd.mir56 ; CHECK: [[FADD:%[0-9]+]]:_(<2 x s64>) = G_FADD [[COPY]], [[COPY1]]
58 ; CHECK: [[FADD2:%[0-9]+]]:_(<2 x s64>) = G_FADD [[FADD]], [[FADD1]]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix64-cc-abi-vaarg.ll236 ; 64BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implic…
237 ; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
238 ; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implic…
323 ; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, impl…
324 ; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, impl…
325 ; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, impl…
326 ; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f5, impl…
327 ; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f6, impl…
328 ; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f7, impl…
335 ; 64BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f1, renamable $f0, implicit $rm
[all …]
H A Daix32-cc-abi-vaarg.ll366 ; 32BIT-DAG: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implic…
367 ; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implic…
368 ; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implic…
369 ; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f4, implic…
370 ; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f5, implic…
371 ; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f6, implic…
372 ; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f7, implic…
373 ; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f8, implic…
374 ; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f9, implic…
385 ; 32BIT-DAG: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implic…
[all …]
H A Daix-p8vector-liveins.ll110 ; NOVSX: %5:f8rc = nofpexcept FADD %0, %1, implicit $rm
111 ; NOVSX: %6:f8rc = nofpexcept FADD killed %5, %2, implicit $rm
112 ; NOVSX: %7:f8rc = nofpexcept FADD killed %6, %3, implicit $rm
113 ; NOVSX: %8:f8rc = nofpexcept FADD killed %7, %4, implicit $rm
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfloat_arithmetic_operations.mir29 ; FP32: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
30 ; FP32: $f0 = COPY [[FADD]](s32)
36 ; FP64: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
37 ; FP64: $f0 = COPY [[FADD]](s32)
145 ; FP32: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
146 ; FP32: $d0 = COPY [[FADD]](s64)
152 ; FP64: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
153 ; FP64: $d0 = COPY [[FADD]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfloat_arithmetic_operations.mir30 ; FP32: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
31 ; FP32: $f0 = COPY [[FADD]](s32)
37 ; FP64: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
38 ; FP64: $f0 = COPY [[FADD]](s32)
150 ; FP32: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY]], [[COPY1]]
151 ; FP32: $d0 = COPY [[FADD]](s64)
157 ; FP64: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY]], [[COPY1]]
158 ; FP64: $d0 = COPY [[FADD]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dlegalize-fadd-scalar.mir41 ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[TRUNC]], [[TRUNC1]]
42 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FADD]](s32)
80 ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[TRUNC]], [[TRUNC1]]
81 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FADD]](s64)
/llvm-project-15.0.7/llvm/test/MachineVerifier/
H A Dtest_vector_reductions.mir28 ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction requires a scalar 1st operand
31 ; CHECK: Bad machine code: Sequential FADD/FMUL vector reduction must have a vector 2nd operand
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dscalable-const-fp-splat.ll5 …; CHECK-NEXT: %[[FADD:.*]] = fadd <vscale x 2 x float> %a, shufflevector (<vscale x 2 x float> in…
6 ; CHECK-NEXT: ret <vscale x 2 x float> %[[FADD]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-masked-loadstore.ll12 ; CHECK-NEXT: %[[FADD:.*]] = fadd <vscale x 4 x float> %[[LOAD1]], %[[LOAD2]]
14 ; CHECK-NEXT: call void @llvm.masked.store.nxv4f32.p0nxv4f32(<vscale x 4 x float> %[[FADD]], <vsca…
49 ; CHECK-NEXT: %[[FADD:.*]] = add <vscale x 4 x i32> %[[LOAD1]], %[[LOAD2]]
51 ; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> %[[FADD]], <vscale…
H A Dvector-reverse.ll19 ; CHECK-NEXT: %[[FADD:.*]] = fadd <8 x double> %[[REVERSE]]
21 ; CHECK-NEXT: %[[REVERSE6:.*]] = shufflevector <8 x double> %[[FADD]], <8 x double> poison, <8 x i3…
54 ; CHECK-NEXT: %[[FADD:.*]] = add <8 x i64> %[[REVERSE]]
56 ; CHECK-NEXT: %[[REVERSE6:.*]] = shufflevector <8 x i64> %[[FADD]], <8 x i64> poison, <8 x i32> <i3…
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dannotate-kernel-features-hsa-call.ll750 ; AKF_HSA-NEXT: [[FADD:%.*]] = fadd float [[F]], 1.000000e+00
751 ; AKF_HSA-NEXT: ret float [[FADD]]
757 ; ATTRIBUTOR_HSA-NEXT: ret float [[FADD]]
769 ; AKF_HSA-NEXT: ret float [[FADD]]
775 ; ATTRIBUTOR_HSA-NEXT: ret float [[FADD]]
788 ; AKF_HSA-NEXT: ret float [[FADD]]
794 ; ATTRIBUTOR_HSA-NEXT: ret float [[FADD]]
806 ; AKF_HSA-NEXT: ret float [[FADD]]
812 ; ATTRIBUTOR_HSA-NEXT: ret float [[FADD]]
827 ; AKF_HSA-NEXT: ret float [[FADD]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dscalable-loop-unpredicated-body-scalar-tail.ll21 ; CHECKUF1: %[[FADD:.*]] = fadd <vscale x 4 x double> %wide.load, shufflevector (<vscale x 4 x doub…
24 ; CHECKUF1: store <vscale x 4 x double> %[[FADD]], <vscale x 4 x double>* %[[IDXA_CAST]], align 8
58 ; CHECKUF2: %[[FADD:.*]] = fadd <vscale x 4 x double> %wide.load, shufflevector (<vscale x 4 x doub…
62 ; CHECKUF2: store <vscale x 4 x double> %[[FADD]], <vscale x 4 x double>* %[[IDXA_CAST]], align 8
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/
H A Daggregate_struct_return.ll20 ; MIPS32: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[LOAD]], [[LOAD2]]
22 ; MIPS32: $f0 = COPY [[FADD]](s32)
57 ; MIPS32: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[LOAD]], [[LOAD2]]
59 ; MIPS32: $d0 = COPY [[FADD]](s64)

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