Searched refs:ExtendOpcode (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 403 if (CurrentUse.ExtendOpcode == OpcodeForCandidate || in ChoosePreferredUse()
404 CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
417 CurrentUse.ExtendOpcode != TargetOpcode::G_ANYEXT) in ChoosePreferredUse()
419 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT && in ChoosePreferredUse()
426 if (CurrentUse.ExtendOpcode == TargetOpcode::G_SEXT && in ChoosePreferredUse()
429 else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ZEXT && in ChoosePreferredUse()
591 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT in applyCombineExtendingLoads()
593 : Preferred.ExtendOpcode == TargetOpcode::G_ZEXT in applyCombineExtendingLoads()
608 if (UseMI->getOpcode() == Preferred.ExtendOpcode || in applyCombineExtendingLoads()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 50 unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT member
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 14153 unsigned ExtendOpcode = Extend.getOpcode(); in performBuildShuffleExtendCombine() local
14154 bool IsSExt = ExtendOpcode == ISD::SIGN_EXTEND || in performBuildShuffleExtendCombine()
14155 ExtendOpcode == ISD::SIGN_EXTEND_INREG || in performBuildShuffleExtendCombine()
14156 ExtendOpcode == ISD::AssertSext; in performBuildShuffleExtendCombine()
14157 if (!IsSExt && ExtendOpcode != ISD::ZERO_EXTEND && in performBuildShuffleExtendCombine()
14158 ExtendOpcode != ISD::AssertZext && ExtendOpcode != ISD::AND) in performBuildShuffleExtendCombine()
14163 ExtendOpcode != ISD::SIGN_EXTEND && ExtendOpcode != ISD::ZERO_EXTEND) in performBuildShuffleExtendCombine()
21163 unsigned ExtendOpcode = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerFixedLengthVectorIntDivideToSVE() local
21164 SDValue Op0 = DAG.getNode(ExtendOpcode, dl, WidenedVT, Op.getOperand(0)); in LowerFixedLengthVectorIntDivideToSVE()
21165 SDValue Op1 = DAG.getNode(ExtendOpcode, dl, WidenedVT, Op.getOperand(1)); in LowerFixedLengthVectorIntDivideToSVE()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 51582 unsigned ExtendOpcode = Extend->getOpcode(); in combineToExtendCMOV() local
51599 if (VT != MVT::i16 && !(ExtendOpcode == ISD::SIGN_EXTEND && VT == MVT::i32)) in combineToExtendCMOV()
51605 if (TargetVT == MVT::i64 && ExtendOpcode != ISD::SIGN_EXTEND) in combineToExtendCMOV()
51608 CMovOp0 = DAG.getNode(ExtendOpcode, DL, ExtendVT, CMovOp0); in combineToExtendCMOV()
51609 CMovOp1 = DAG.getNode(ExtendOpcode, DL, ExtendVT, CMovOp1); in combineToExtendCMOV()
51616 Res = DAG.getNode(ExtendOpcode, DL, TargetVT, Res); in combineToExtendCMOV()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 10818 auto ExtendOpcode = AllAddOne ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in foldVSelectOfConstants() local
10819 SDValue ExtendedCond = DAG.getNode(ExtendOpcode, DL, VT, Cond); in foldVSelectOfConstants()
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