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Searched refs:ExtReg (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/bolt/lib/Passes/
H A DRegReAssign.cpp274 MCPhysReg ExtReg = *Begin; in aggressivePassOverFunction() local
275 if (!Extended[ExtReg] || RegScore[ExtReg] <= 0) { in aggressivePassOverFunction()
280 if (RegScore[ClassicReg] << 1 >= RegScore[ExtReg]) { in aggressivePassOverFunction()
282 << " with " << BC.MRI->getName(ExtReg) in aggressivePassOverFunction()
291 << " with " << BC.MRI->getName(ExtReg) in aggressivePassOverFunction()
297 AnyAliasAlive &= BC.MIB->getAliases(ExtReg); in aggressivePassOverFunction()
300 << " with " << BC.MRI->getName(ExtReg) in aggressivePassOverFunction()
308 << " with " << BC.MRI->getName(ExtReg) << "\n\n"); in aggressivePassOverFunction()
309 swap(Function, ClassicReg, ExtReg); in aggressivePassOverFunction()
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp41 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
42 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
48 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
52 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallLowering.cpp110 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
111 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
117 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
121 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
H A DX86FastISel.cpp1092 Register ExtReg = createResultReg(&X86::GR64RegClass); in X86SelectCallAddress() local
1094 TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) in X86SelectCallAddress()
1098 Reg = ExtReg; in X86SelectCallAddress()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp120 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
121 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
127 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
130 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp222 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
223 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
254 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
255 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp65 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
74 {MRI.getType(ExtReg)}, false) in assignValueToReg()
75 .addReg(ExtReg); in assignValueToReg()
76 ExtReg = ToSGPR.getReg(0); in assignValueToReg()
79 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
221 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
222 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
H A DAMDGPUInstructionSelector.cpp2149 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); in selectG_SZA_EXT() local
2154 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) in selectG_SZA_EXT()
2161 .addReg(ExtReg) in selectG_SZA_EXT()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp932 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
933 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
935 SrcReg1 = ExtReg; in PPCEmitCmp()
938 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
939 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
941 SrcReg2 = ExtReg; in PPCEmitCmp()
H A DPPCISelLowering.cpp11462 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary() local
11464 ExtReg).addReg(dest); in EmitAtomicBinary()
11466 .addReg(incr).addReg(ExtReg); in EmitAtomicBinary()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp288 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
289 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
H A DAArch64InstructionSelector.cpp6348 Register ExtReg = moveScalarRegClass(OffsetInst->getOperand(1).getReg(), in selectAddrModeWRO() local
6354 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
6643 Register ExtReg; in selectArithExtendedRegister() local
6670 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
6676 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
6682 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) { in selectArithExtendedRegister()
6683 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg); in selectArithExtendedRegister()
6692 ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB); in selectArithExtendedRegister()
6694 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectArithExtendedRegister()