Searched refs:ExecReg (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 91 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in optimizeVccBranch() local
103 if (A->modifiesRegister(ExecReg, TRI)) in optimizeVccBranch()
118 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
122 if (Op1.getReg() != ExecReg) in optimizeVccBranch()
140 ModifiesExec |= M->modifiesRegister(ExecReg, TRI); in optimizeVccBranch()
182 .addReg(ExecReg); in optimizeVccBranch()
190 if (SReg == ExecReg) { in optimizeVccBranch()
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| H A D | SIOptimizeExecMaskingPreRA.cpp | 40 MCRegister ExecReg; member in __anon6b0c42990111::SIOptimizeExecMaskingPreRA
140 if (CmpReg == Register(ExecReg)) { in optimizeVcndVcmpPair()
144 } else if (And->getOperand(2).getReg() != Register(ExecReg)) { in optimizeVcndVcmpPair()
204 .addReg(ExecReg) in optimizeVcndVcmpPair()
328 if (XorTermMI.getOperand(1).getReg() != Register(ExecReg)) in optimizeElseBranch()
339 I->getOperand(1).getReg() == Register(ExecReg)) in optimizeElseBranch()
352 for (MCRegUnitIterator UI(ExecReg, TRI); UI.isValid(); ++UI) { in optimizeElseBranch()
389 ExecReg = MCRegister::from(Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC); in runOnMachineFunction()
482 if (!(I->isFullCopy() && I->getOperand(1).getReg() == Register(ExecReg))) in runOnMachineFunction()
496 MRI->replaceRegWith(SavedExec, ExecReg); in runOnMachineFunction()
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| H A D | SILowerI1Copies.cpp | 55 unsigned ExecReg; member in __anone83803c50111::SILowerI1Copies
459 ExecReg = AMDGPU::EXEC_LO; in runOnMachineFunction()
467 ExecReg = AMDGPU::EXEC; in runOnMachineFunction()
841 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg); in buildMergeLaneMasks()
844 .addReg(ExecReg) in buildMergeLaneMasks()
859 .addReg(ExecReg); in buildMergeLaneMasks()
870 .addReg(ExecReg); in buildMergeLaneMasks()
883 .addReg(ExecReg); in buildMergeLaneMasks()
887 .addReg(CurMaskedReg ? CurMaskedReg : ExecReg); in buildMergeLaneMasks()
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| H A D | SILateBranchLowering.cpp | 39 Register ExecReg; member in __anon997992fa0111::SILateBranchLowering
142 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
182 ExecReg) in runOnMachineFunction()
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| H A D | SIRegisterInfo.cpp | 108 Register ExecReg; member
130 ExecReg = AMDGPU::EXEC_LO; in SGPRSpillBuilder()
134 ExecReg = AMDGPU::EXEC; in SGPRSpillBuilder()
209 BuildMI(*MBB, MI, DL, TII.get(MovOpc), SavedExecReg).addReg(ExecReg); in prepare()
211 BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg).addImm(VGPRLanes); in prepare()
228 auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in prepare()
252 auto I = BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg) in restore()
263 auto I = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in restore()
302 auto Not0 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
305 auto Not1 = BuildMI(*MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
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| H A D | AMDGPURegisterBankInfo.cpp | 778 const unsigned ExecReg = Subtarget.isWave32() ? in executeInWaterfallLoop() local
940 .addDef(ExecReg) in executeInWaterfallLoop()
941 .addReg(ExecReg) in executeInWaterfallLoop()
952 .addReg(ExecReg); in executeInWaterfallLoop()
957 .addDef(ExecReg) in executeInWaterfallLoop()
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