| /llvm-project-15.0.7/llvm/test/Transforms/Attributor/IPConstantProp/ |
| H A D | naked-return.ll | 15 ; CHECK-NEXT: call void asm "\0D\0Apushl %ebp\0D\0Amovl 8([[ESP:%.*]]),%eax\0D\0Amovl 12([[ESP]]… 28 …ECK-NEXT: call void asm "\0D\0A movl 12([[ESP:%.*]]), %ebp\0D\0A movl 4([[ESP]]), %eax\0D\0A mo…
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| /llvm-project-15.0.7/llvm/test/MC/X86/ |
| H A D | i386-darwin-frame-register.ll | 8 ; In the debug_frame mapping, register 4 is ESP, thus the below tests that 9 ; the CFA is ESP+4 upon function entry. 14 ; CHECK: DW_CFA_def_cfa: ESP +4
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| /llvm-project-15.0.7/llvm/test/DebugInfo/COFF/ |
| H A D | fpo-realign-vframe.ll | 7 ; compiler will address locals with the ESP register. However, if call argument 8 ; set up uses PUSH instructions, ESP may vary over the course of the function. 61 ; 'x' should be EBP-relative, 'a' and 'force_alignment' ESP relative. 121 ; ESP is VFRAME - 16, ESP offset of 'a' is 4, so -12. 133 ; ESP is VFRAME - 16, ESP offset of 'force_alignment' is 8, so -8.
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| H A D | vframe-csr.ll | 24 ; 'x' should be EBP-relative, 'a' and 'force_alignment' ESP relative. 73 ; ESP is VFRAME - 24, ESP offset of 'a' is 4, so -20. 85 ; ESP is VFRAME - 16, ESP offset of 'force_alignment' is 8, so -8.
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| /llvm-project-15.0.7/llvm/test/ExecutionEngine/MCJIT/ |
| H A D | 2003-08-23-RegisterAllocatePhysReg.ll | 6 ; use the ESP register (which is not allocatable) to hold a value. 9 ; ESP gets used again...
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | win32-seh-catchpad-realign.ll | 51 ; Spill ESP 69 ; Restore ESP
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| H A D | physreg-pairs.ll | 7 ; ECX, EBX, ESI, EDI, EBP, ESP, to the value. There is no wrapping 8 ; from the sequence, so this will fail given ESP.
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| H A D | cleanuppad-inalloca.ll | 46 ; ESP must be restored via EBP due to "dynamic" alloca.
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| H A D | shrink-wrap-chkstk.ll | 6 ; chkstk cannot come before the usual prologue, since it adjusts ESP.
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| H A D | seh-except-restore.ll | 4 ; before the instructions that restore EBP and ESP back to what they should be.
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| H A D | seh-stack-realign.ll | 62 ; Restore ESP
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| /llvm-project-15.0.7/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfCFIException.cpp | 122 ExceptionSymbolProvider ESP) { in beginFragment() argument 160 Asm->OutStreamer->emitCFILsda(ESP(Asm, MBB), TLOF.getLSDAEncoding()); in beginFragment()
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| H A D | DwarfException.h | 65 ExceptionSymbolProvider ESP) override;
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| /llvm-project-15.0.7/llvm/include/llvm/Support/Solaris/sys/ |
| H A D | regset.h | 28 #undef ESP
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | AsmPrinterHandler.h | 61 ExceptionSymbolProvider ESP) {} in beginFragment() argument
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| /llvm-project-15.0.7/llvm/test/DebugInfo/ |
| H A D | dwarfdump-debug-frame-simple.test | 9 ; FRAMES: DW_CFA_def_cfa: {{reg4|ESP}} +4
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 199 {codeview::RegisterId::ESP, X86::ESP}, in initLLVMToSEHAndCVRegMapping() 453 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; in createX86MCAsmInfo() 755 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero() 783 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero() 820 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero() 856 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero() 857 return X86::ESP; in getX86SubSuperRegisterOrZero() 892 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
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| H A D | X86MCTargetDesc.h | 51 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 enumerator
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.td | 150 def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>; 176 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; 421 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, 461 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>; 481 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; 486 // GR32_NOSP - GR32 registers except ESP. 487 def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; 493 // ESP. 533 def GR32_BPSP : RegisterClass<"X86", [i32], 32, (add EBP, ESP)>;
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| H A D | X86InstrControl.td | 219 // All calls clobber the non-callee saved registers. ESP is marked as 223 let Uses = [ESP, SSP] in { 291 isCodeGenOnly = 1, Uses = [ESP, SSP] in { 314 let Uses = [ESP, EFLAGS, SSP] in {
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| H A D | X86IndirectThunks.cpp | 246 const Register SPReg = Is64Bit ? X86::RSP : X86::ESP; in populateThunk()
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| H A D | X86RegisterInfo.cpp | 68 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo() 73 StackPtr = X86::ESP; in X86RegisterInfo() 906 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP) in findDeadCallerSavedReg()
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| H A D | X86FixupLEAs.cpp | 577 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA() 665 if (p.isReg() && p.getReg() != X86::ESP) { in processInstruction() 669 if (q.isReg() && q.getReg() != X86::ESP) { in processInstruction()
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| H A D | X86InstrCompiler.td | 29 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP], 34 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into 39 let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in { 106 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 123 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 151 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in 454 // All calls clobber the non-callee saved registers. ESP is marked as 462 usesCustomInserter = 1, Uses = [ESP, SSP] in { 506 Uses = [ESP, SSP],
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| H A D | X86FrameLowering.cpp | 1143 unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP; in emitStackProbeCall() 1951 .addReg(X86::ESP); in emitPrologue() 2240 TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true); in emitEpilogue() 2983 ScratchReg = IsLP64 ? X86::RSP : X86::ESP; in adjustForSegmentedStacks() 3010 ScratchReg = X86::ESP; in adjustForSegmentedStacks() 3012 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP) in adjustForSegmentedStacks() 3284 SPReg = X86::ESP; in adjustForHiPEPrologue() 3581 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP), in restoreWin32EHStackPointers()
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